Lines Matching +full:0 +full:xe0004000

13 		#size-cells = <0>;
15 		cpu0: cpu@0 {
18 			reg = <0>;
47 		interrupts = <0 5 4>, <0 6 4>;
49 		reg = <0xf8891000 0x1000>,
50 		      <0xf8893000 0x1000>;
69 			#size-cells = <0>;
72 			port@0 {
73 				reg = <0>;
104 			reg = <0xf8007100 0x20>;
105 			interrupts = <0 7 4>;
115 			reg = <0xe0008000 0x1000>;
116 			interrupts = <0 28 4>;
118 			tx-fifo-depth = <0x40>;
119 			rx-fifo-depth = <0x40>;
127 			reg = <0xe0009000 0x1000>;
128 			interrupts = <0 51 4>;
130 			tx-fifo-depth = <0x40>;
131 			rx-fifo-depth = <0x40>;
142 			interrupts = <0 20 4>;
143 			reg = <0xe000a000 0x1000>;
151 			interrupts = <0 25 4>;
152 			reg = <0xe0004000 0x1000>;
154 			#size-cells = <0>;
162 			interrupts = <0 48 4>;
163 			reg = <0xe0005000 0x1000>;
165 			#size-cells = <0>;
172 			reg = <0xF8F01000 0x1000>,
173 			      <0xF8F00100 0x100>;
178 			reg = <0xF8F02000 0x1000>;
179 			interrupts = <0 2 4>;
188 			reg = <0xf8006000 0x1000>;
196 			reg = <0xE0000000 0x1000>;
197 			interrupts = <0 27 4>;
205 			reg = <0xE0001000 0x1000>;
206 			interrupts = <0 50 4>;
211 			reg = <0xe0006000 0x1000>;
214 			interrupts = <0 26 4>;
218 			#size-cells = <0>;
223 			reg = <0xe0007000 0x1000>;
226 			interrupts = <0 49 4>;
230 			#size-cells = <0>;
235 			reg = <0xe000b000 0x1000>;
237 			interrupts = <0 22 4>;
241 			#size-cells = <0>;
246 			reg = <0xe000c000 0x1000>;
248 			interrupts = <0 45 4>;
252 			#size-cells = <0>;
261 			interrupts = <0 24 4>;
262 			reg = <0xe0100000 0x1000>;
271 			interrupts = <0 47 4>;
272 			reg = <0xe0101000 0x1000>;
279 			reg = <0xF8000000 0x1000>;
284 				fclk-enable = <0>;
296 				reg = <0x100 0x100>;
301 				reg = <0x200 0x48>;
308 				reg = <0x700 0x200>;
315 			reg = <0xf8003000 0x1000>;
319 			interrupts = <0 13 4>,
320 			             <0 14 4>, <0 15 4>,
321 			             <0 16 4>, <0 17 4>,
322 			             <0 40 4>, <0 41 4>,
323 			             <0 42 4>, <0 43 4>;
333 			reg = <0xf8007000 0x100>;
335 			interrupts = <0 8 4>;
343 			reg = <0xf8f00200 0x20>;
344 			interrupts = <1 11 0x301>;
351 			interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
354 			reg = <0xF8001000 0x1000>;
359 			interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
362 			reg = <0xF8002000 0x1000>;
367 			interrupts = <1 13 0x301>;
369 			reg = <0xf8f00600 0x20>;
378 			interrupts = <0 21 4>;
379 			reg = <0xe0002000 0x1000>;
388 			interrupts = <0 44 4>;
389 			reg = <0xe0003000 0x1000>;
397 			interrupts = <0 9 1>;
398 			reg = <0xf8005000 0x1000>;
404 			reg = <0xf8801000 0x1000>;
418 			reg = <0xf8803000 0x1000>;
432 			reg = <0xf8804000 0x1000>;
448 				#size-cells = <0>;
451 				port@0 {
452 					reg = <0>;
476 			reg = <0xf889c000 0x1000>;
491 			reg = <0xf889d000 0x1000>;