Lines Matching +full:0 +full:x100
12 #define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */
15 #define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */
17 #define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
19 #define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
21 #define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
23 #define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
25 #define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
27 #define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
29 #define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
31 #define SMC_MEMC_STATUS_OFFSET 0x000
32 #define SMC_MEMIF_CFG_OFFSET 0x004
33 #define SMC_MEMC_CFG_SET_OFFSET 0x008
34 #define SMC_MEMC_CFG_CLR_OFFSET 0x00C
35 #define SMC_DIRECT_CMD_OFFSET 0x010
36 #define SMC_SET_CYCLES_OFFSET 0x014
37 #define SMC_SET_OPMODE_OFFSET 0x018
38 #define SMC_REFRESH_PERIOD_0_OFFSET 0x020
39 #define SMC_REFRESH_PERIOD_1_OFFSET 0x024
40 #define SMC_SRAM_CYCLES0_0_OFFSET 0x100
41 #define SMC_NAND_CYCLES0_0_OFFSET 0x100
42 #define SMC_OPMODE0_0_OFFSET 0x104
43 #define SMC_SRAM_CYCLES0_1_OFFSET 0x120
44 #define SMC_NAND_CYCLES0_1_OFFSET 0x120
45 #define SMC_OPMODE0_1_OFFSET 0x124
46 #define SMC_USER_STATUS_OFFSET 0x200
47 #define SMC_USER_CONFIG_OFFSET 0x204
48 #define SMC_ECC_STATUS_OFFSET 0x300
49 #define SMC_ECC_MEMCFG_OFFSET 0x304
50 #define SMC_ECC_MEMCOMMAND1_OFFSET 0x308
51 #define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C
52 #define SMC_ECC_ADDR0_OFFSET 0x310
53 #define SMC_ECC_ADDR1_OFFSET 0x314
54 #define SMC_ECC_VALUE0_OFFSET 0x318
55 #define SMC_ECC_VALUE1_OFFSET 0x31C
56 #define SMC_ECC_VALUE2_OFFSET 0x320
57 #define SMC_ECC_VALUE3_OFFSET 0x324
58 #define SMC_PERIPH_ID_0_OFFSET 0xFE0
59 #define SMC_PERIPH_ID_1_OFFSET 0xFE4
60 #define SMC_PERIPH_ID_2_OFFSET 0xFE8
61 #define SMC_PERIPH_ID_3_OFFSET 0xFEC
62 #define SMC_PCELL_ID_0_OFFSET 0xFF0
63 #define SMC_PCELL_ID_1_OFFSET 0xFF4
64 #define SMC_PCELL_ID_2_OFFSET 0xFF8
65 #define SMC_PCELL_ID_3_OFFSET 0xFFC
67 #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
69 #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
71 #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
73 #define RTC_SEC_OFFSET 0x00
74 #define RTC_MIN_OFFSET 0x04
75 #define RTC_HOUR_OFFSET 0x08
76 #define RTC_DAY_OFFSET 0x0C
77 #define RTC_SEC_ALM_OFFSET 0x10
78 #define RTC_MIN_ALM_OFFSET 0x14
79 #define RTC_HOUR_ALM_OFFSET 0x18
80 #define RTC_REC_OFFSET 0x1C
81 #define RTC_CTRL_OFFSET 0x20
82 #define RTC_INTR_STS_OFFSET 0x34
84 #define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
85 #define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */
87 #define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
88 #define CNS3XXX_PM_BASE_VIRT 0xFB001000
90 #define PM_CLK_GATE_OFFSET 0x00
91 #define PM_SOFT_RST_OFFSET 0x04
92 #define PM_HS_CFG_OFFSET 0x08
93 #define PM_CACTIVE_STA_OFFSET 0x0C
94 #define PM_PWR_STA_OFFSET 0x10
95 #define PM_SYS_CLK_CTRL_OFFSET 0x14
96 #define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18
97 #define PM_PLL_HM_PD_OFFSET 0x1C
99 #define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
100 #define CNS3XXX_UART0_BASE_VIRT 0xFB002000
102 #define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
104 #define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
106 #define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
108 #define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
110 #define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
112 #define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
114 #define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
115 #define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
117 #define TIMER1_COUNTER_OFFSET 0x00
118 #define TIMER1_AUTO_RELOAD_OFFSET 0x04
119 #define TIMER1_MATCH_V1_OFFSET 0x08
120 #define TIMER1_MATCH_V2_OFFSET 0x0C
122 #define TIMER2_COUNTER_OFFSET 0x10
123 #define TIMER2_AUTO_RELOAD_OFFSET 0x14
124 #define TIMER2_MATCH_V1_OFFSET 0x18
125 #define TIMER2_MATCH_V2_OFFSET 0x1C
127 #define TIMER1_2_CONTROL_OFFSET 0x30
128 #define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34
129 #define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38
131 #define TIMER_FREERUN_OFFSET 0x40
132 #define TIMER_FREERUN_CONTROL_OFFSET 0x44
134 #define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
136 #define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
138 #define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
140 #define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
142 #define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
144 #define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
146 #define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
149 #define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
151 #define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
153 #define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
155 #define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
157 #define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
159 #define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
161 #define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
163 #define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */
164 #define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000
166 #define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */
168 #define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */
169 #define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000
171 #define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */
172 #define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000
174 #define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */
176 #define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */
178 #define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */
179 #define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000
181 #define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */
183 #define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */
184 #define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000
186 #define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */
187 #define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000
189 #define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */
194 #define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
195 #define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000
197 #define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
198 #define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
200 #define CNS3XXX_TC11MP_TWD_BASE 0x90000600
201 #define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
203 #define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
204 #define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
206 #define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
213 #define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00)
214 #define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04)
215 #define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08)
216 #define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C)
217 #define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10)
218 #define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14)
219 #define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18)
220 #define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C)
221 #define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20)
222 #define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24)
223 #define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28)
224 #define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C)
225 #define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30)
226 #define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34)
227 #define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40)
228 #define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44)
229 #define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48)
230 #define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C)
231 #define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50)
232 #define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54)
234 #define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310)
236 #define MISC_USB_CFG_REG MISC_MEM_MAP(0x800)
237 #define MISC_USB_STS_REG MISC_MEM_MAP(0x804)
238 #define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808)
239 #define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c)
240 #define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810)
241 #define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814)
243 #define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
244 #define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
245 #define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100)
246 #define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100)
247 #define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100)
248 #define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100)
249 #define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100)
250 #define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100)
251 #define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100)
252 #define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100)
253 #define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100)
254 #define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100)
255 #define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100)
256 #define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100)
257 #define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100)
258 #define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
259 #define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
266 #define PM_CLK_GATE_REG PMU_MEM_MAP(0x000)
267 #define PM_SOFT_RST_REG PMU_MEM_MAP(0x004)
268 #define PM_HS_CFG_REG PMU_MEM_MAP(0x008)
269 #define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C)
270 #define PM_PWR_STA_REG PMU_MEM_MAP(0x010)
271 #define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014)
272 #define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018)
273 #define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C)
274 #define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020)
275 #define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024)
276 #define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028)
277 #define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C)
278 #define PM_CSR_REG PMU_MEM_MAP(0x030)
303 #define PM_CLK_GATE_REG_MASK (0x03FFFFBA)
332 #define PM_SOFT_RST_REG_OFFST_GLOBAL (0)
333 #define PM_SOFT_RST_REG_MASK (0xF3FFFFBF)
360 #define PM_HS_CFG_REG_MASK (0x03FFFFBE)
361 #define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806)
388 #define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE)
415 #define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE)
433 #define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0)
436 PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
437 PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
441 PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
442 PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
450 #define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0)
460 #define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C)
463 #define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0)
467 #define PM_CSR_REG_OFFSET_CSR_NUM (0)
469 #define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK)
472 #define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK)
478 #define CNS3XXX_PWR_CPU_MODE_DFS (0)
485 #define CNS3XXX_PWR_PLL(BLOCK) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK)
489 #define CNS3XXX_PWR_PLL_CPU_300MHZ (0)
503 #define CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0)
508 #define CNS3XXX_PWR_PLL_DDR2_200MHZ (0)
522 #define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)