Lines Matching refs:ldr
22 ldr r0, =PSSR
26 ldr ip, [r3]
62 ldr r2, [r1] @ Dummy read PXA3_MDCNFG
69 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
72 1: ldr r0, [r1, #PXA3_DDR_HCAL]
76 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
83 ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
87 ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
92 1: ldr r0, [r1, #PXA3_DMCISR]
96 ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
99 1: ldr r0, [r1, #PXA3_MDCNFG]
103 ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
107 ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt