Lines Matching +full:0 +full:x01800000
14 #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
28 #define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
32 #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
33 #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
35 #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
36 #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
38 #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
39 #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
41 #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
42 #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
46 #define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
47 #define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000)
49 #define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
50 #define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000)
52 #define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
53 #define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
56 * 0xE0000000 contains the IO space that is split by speed and
60 * 0x10000000 of space, partitioned as so:
62 * 0x00000000 to 0x04000000 8bit, slow
63 * 0x04000000 to 0x08000000 16bit, slow
64 * 0x08000000 to 0x0C000000 16bit, net
65 * 0x0C000000 to 0x10000000 16bit, fast
69 * 0x02000000 to 0x02100000 1MB IDE primary channel
70 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
71 * 0x02200000 to 0x02400000 1MB IDE secondary channel
72 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
73 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers
74 * 0x02600000 to 0x02700000 1MB
83 #define VR1000_VA_MULTISPACE (0xE0000000)
85 #define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000)
86 #define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000)
87 #define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000)
88 #define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
89 #define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000)
90 #define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
91 #define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000)
92 #define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000)
93 #define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000)
97 #define VR1000_PA_IDEPRI (0x02000000)
98 #define VR1000_PA_IDEPRIAUX (0x02800000)
99 #define VR1000_PA_IDESEC (0x03000000)
100 #define VR1000_PA_IDESECAUX (0x03800000)
101 #define VR1000_PA_DM9000 (0x05000000)
103 #define VR1000_PA_SERIAL (0x11800000)
104 #define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000))
107 #define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000)