36 static void tegra_secondary_init(unsigned int cpu)  in tegra_secondary_init()  argument
38 	cpumask_set_cpu(cpu, &tegra_cpu_init_mask);  in tegra_secondary_init()
42 static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle)  in tegra20_boot_secondary()  argument
44 	cpu = cpu_logical_map(cpu);  in tegra20_boot_secondary()
47 	 * Force the CPU into reset. The CPU must remain in reset when  in tegra20_boot_secondary()
49 	 * flow controller to stop driving reset if the CPU has been  in tegra20_boot_secondary()
51 	 * effect on first boot of the CPU since it should already be  in tegra20_boot_secondary()
54 	tegra_put_cpu_in_reset(cpu);  in tegra20_boot_secondary()
57 	 * Unhalt the CPU. If the flow controller was used to  in tegra20_boot_secondary()
58 	 * power-gate the CPU this will cause the flow controller to  in tegra20_boot_secondary()
59 	 * stop driving reset. The CPU will remain in reset because the  in tegra20_boot_secondary()
62 	flowctrl_write_cpu_halt(cpu, 0);  in tegra20_boot_secondary()
64 	tegra_enable_cpu_clock(cpu);  in tegra20_boot_secondary()
65 	flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */  in tegra20_boot_secondary()
66 	tegra_cpu_out_of_reset(cpu);  in tegra20_boot_secondary()
70 static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)  in tegra30_boot_secondary()  argument
75 	cpu = cpu_logical_map(cpu);  in tegra30_boot_secondary()
76 	tegra_put_cpu_in_reset(cpu);  in tegra30_boot_secondary()
77 	flowctrl_write_cpu_halt(cpu, 0);  in tegra30_boot_secondary()
80 	 * The power up sequence of cold boot CPU and warm boot CPU  in tegra30_boot_secondary()
83 	 * For warm boot CPU that was resumed from CPU hotplug, the  in tegra30_boot_secondary()
85 	 * flow controller of the warm boot CPU. We need to wait for  in tegra30_boot_secondary()
86 	 * the confirmaiton that the CPU is powered then removing  in tegra30_boot_secondary()
88 	 * For cold boot CPU, do not wait. After the cold boot CPU be  in tegra30_boot_secondary()
93 	if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {  in tegra30_boot_secondary()
96 			if (tegra_pmc_cpu_is_powered(cpu))  in tegra30_boot_secondary()
103 	 * The power status of the cold boot CPU is power gated as  in tegra30_boot_secondary()
104 	 * default. To power up the cold boot CPU, the power should  in tegra30_boot_secondary()
108 	ret = tegra_pmc_cpu_power_on(cpu);  in tegra30_boot_secondary()
113 	/* CPU partition is powered. Enable the CPU clock. */  in tegra30_boot_secondary()
114 	tegra_enable_cpu_clock(cpu);  in tegra30_boot_secondary()
118 	ret = tegra_pmc_cpu_remove_clamping(cpu);  in tegra30_boot_secondary()
124 	flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */  in tegra30_boot_secondary()
125 	tegra_cpu_out_of_reset(cpu);  in tegra30_boot_secondary()
129 static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)  in tegra114_boot_secondary()  argument
133 	cpu = cpu_logical_map(cpu);  in tegra114_boot_secondary()
135 	if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {  in tegra114_boot_secondary()
139 		 * control for each CPU.  in tegra114_boot_secondary()
142 		flowctrl_write_cpu_csr(cpu, 1);  in tegra114_boot_secondary()
143 		flowctrl_write_cpu_halt(cpu,  in tegra114_boot_secondary()
148 		 * The CPU is powered up by toggling PMC directly. It will  in tegra114_boot_secondary()
150 		 * the CPU's power state is maintained by flow controller.  in tegra114_boot_secondary()
152 		ret = tegra_pmc_cpu_power_on(cpu);  in tegra114_boot_secondary()
158 static int tegra_boot_secondary(unsigned int cpu,  in tegra_boot_secondary()  argument
162 		return tegra20_boot_secondary(cpu, idle);  in tegra_boot_secondary()
164 		return tegra30_boot_secondary(cpu, idle);  in tegra_boot_secondary()
166 		return tegra114_boot_secondary(cpu, idle);  in tegra_boot_secondary()
168 		return tegra114_boot_secondary(cpu, idle);  in tegra_boot_secondary()
175 	/* Always mark the boot CPU (CPU0) as initialized. */  in tegra_smp_prepare_cpus()