Lines Matching +full:cortex +full:- +full:a57
1 # SPDX-License-Identifier: GPL-2.0-only
164 if $(cc-option,-fpatchable-function-entry=2)
211 ARM 64-bit (AArch64) Linux support.
243 # VA_BITS - PAGE_SHIFT - 3
336 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
363 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
368 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
371 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
377 data cache clean-and-invalidate.
385 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
390 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
399 data cache clean-and-invalidate.
407 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
412 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
415 If a Cortex-A53 processor is executing a store or prefetch for
422 data cache clean-and-invalidate.
430 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
435 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
444 data cache clean-and-invalidate.
452 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
456 erratum 832075 on Cortex-A57 parts up to r1p2.
458 Affected Cortex-A57 parts might deadlock when exclusive load/store
459 instructions to Write-Back memory are mixed with Device loads.
461 The workaround is to promote device loads to use Load-Acquire
470 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
475 erratum 834220 on Cortex-A57 parts up to r1p2.
477 Affected Cortex-A57 parts might report a Stage 2 translation
491 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
495 This option removes the AES hwcap for aarch32 user-space to
496 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
507 bool "Cortex-A53: 845719: a load might read incorrect data"
512 erratum 845719 on Cortex-A53 parts up to r0p4.
514 When running a compat (AArch32) userspace on an affected Cortex-A53
520 return to a 32-bit task.
528 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
532 This option links the kernel with '--fix-cortex-a53-843419' and
535 Cortex-A53 parts up to r0p4.
540 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
543 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
545 Affected Cortex-A55 cores (all revisions) could cause incorrect
547 without a break-before-make. The workaround is to disable the usage
554 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
558 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
561 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
571 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
575 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
577 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
584 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
588 This option adds work arounds for ARM Cortex-A57 erratum 1319537
591 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
597 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
601 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
603 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
613 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
617 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
619 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
623 break-before-make sequence, then under very rare circumstances
629 bool "Cortex-A76: Software Step might prevent interrupt recognition"
632 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
634 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
647 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
650 This option adds a workaround for ARM Neoverse-N1 erratum
653 Affected Neoverse-N1 cores could execute a stale instruction when
658 forces user-space to perform cache maintenance.
663 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
666 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
668 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
669 of a store-exclusive or read of PAR_EL1 and a load with device or
670 non-cacheable memory attributes. The workaround depends on a firmware
683 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
687 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
690 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
706 This implements two gicv3-its errata workarounds for ThunderX. Both
742 contains data for a non-current ASID. The fix is to
753 interrupts in host. Trapping both GICv3 group-0 and group-1
776 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
779 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
780 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
784 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
785 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
786 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
787 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
790 The workaround only affects the Fujitsu-A64FX.
847 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
851 MSI doorbell writes with non-zero values for the device ID.
881 look-up. AArch32 emulation requires applications compiled
897 bool "36-bit" if EXPERT
901 bool "39-bit"
905 bool "42-bit"
909 bool "47-bit"
913 bool "48-bit"
916 bool "52-bit"
919 Enable 52-bit virtual addressing for userspace when explicitly
920 requested via a hint to mmap(). The kernel will also use 52-bit
922 this feature is available, otherwise it reverts to 48-bit).
924 NOTE: Enabling 52-bit virtual addressing in conjunction with
927 impact on its susceptibility to brute-force attacks.
929 If unsure, select 48-bit virtual addressing instead.
934 bool "Force 52-bit virtual addresses for userspace"
937 For systems with 52-bit userspace VAs enabled, the kernel will attempt
938 to maintain compatibility with older software by providing 48-bit VAs
941 This configuration option disables the 48-bit compatibility logic, and
942 forces all userspace addresses to be 52-bit on HW that supports it. One
963 bool "48-bit"
966 bool "52-bit (ARMv8.2)"
970 Enable support for a 52-bit physical address space, introduced as
971 part of the ARMv8.2-LPA extension.
974 do not support ARMv8.2-LPA, but with some added memory overhead (and
993 bool "Build big-endian kernel"
996 Say Y if you plan on running a kernel with a big-endian userspace.
999 bool "Build little-endian kernel"
1001 Say Y if you plan on running a kernel with a little-endian userspace.
1007 bool "Multi-core scheduler support"
1009 Multi-core scheduler support improves the CPU scheduler's decision
1010 making when dealing with multi-core CPU chips at a cost of slightly
1021 int "Maximum number of CPUs (2-4096)"
1026 bool "Support for hot-pluggable CPUs"
1038 Enable NUMA (Non-Uniform Memory Access) support.
1103 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1171 loaded in the main kernel with kexec-tools into a specially
1175 For more details see Documentation/admin-guide/kdump/kdump.rst
1207 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1216 Speculation attacks against some high-performance processors can
1228 Speculation attacks against some high-performance processors can
1230 When taking an exception from user-space, a sequence of branches
1237 Apply read-only attributes of VM areas to the linear alias of
1238 the backing pages as well. This prevents code or read-only data
1251 user-space memory directly by pointing TTBR0_EL1 to a reserved
1262 Documentation/arm64/tagged-address-abi.rst.
1265 bool "Kernel support for 32-bit EL0"
1272 This option enables support for a 32-bit EL0 running under a 64-bit
1273 kernel at EL1. AArch32-specific components such as system calls,
1281 If you want to execute 32-bit userspace applications, say Y.
1286 bool "Enable kuser helpers page for 32-bit applications"
1289 Warning: disabling this option may break 32-bit user programs.
1313 bool "Enable vDSO for 32-bit applications"
1319 Place in the process address space of 32-bit applications an
1323 You must have a 32-bit build of glibc 2.22 or later for programs
1327 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1331 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1332 otherwise with '-marm'.
1374 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1375 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1390 The SETEND instruction alters the data-endianness of the
1398 for this feature to be enabled. If a new CPU - which doesn't support mixed
1399 endian - is hotplugged in after this feature has been enabled, there could
1418 Similarly, writes to read-only pages with the DBM bit set will
1419 clear the read-only bit (AP[2]) instead of raising a
1423 to work on pre-ARMv8.1 hardware and the performance impact is
1431 prevents the kernel or hypervisor from accessing user-space (EL0)
1441 def_bool $(as-instr,.arch_extension lse)
1457 Say Y here to make use of these instructions for the in-kernel
1489 variant of the load/store instructions. This ensures that user-space
1494 Choosing this option will cause copy_to_user() et al to use user-space
1565 context-switched along with the process.
1567 If the compiler supports the -mbranch-protection or
1568 -msign-return-address flag (e.g. GCC 7 or later), then this option
1589 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1593 def_bool $(cc-option,-msign-return-address=all)
1596 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1599 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1629 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1636 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1678 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1689 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1713 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1717 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1727 architectural support for run-time, always-on detection of
1729 to eliminate vulnerabilities arising from memory-unsafe
1737 not be allowed a late bring-up.
1743 Documentation/arm64/memory-tagging-extension.rst.
1773 If you need the kernel to boot on SVE-capable hardware with broken
1806 bool "Support for NMI-like interrupts"
1809 Adds support for mimicking Non-Maskable Interrupts through the use of
1853 random u64 value in /chosen/kaslr-seed at kernel entry.
1878 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
1901 Provide a set of default command-line options at build time by
1912 command-line options your boot loader passes to the kernel.
1931 by UEFI firmware (such as non-volatile variables, realtime
1945 continue to boot on existing non-UEFI platforms.