Lines Matching +full:0 +full:x0300a000
21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
71 #clock-cells = <0>;
113 reg = <0x1000000 0x400000>;
117 ranges = <0 0x1000000 0x400000>;
119 display_clocks: clock@0 {
121 reg = <0x0 0x10000>;
132 compatible = "allwinner,sun50i-h6-de3-mixer-0";
133 reg = <0x100000 0x100000>;
139 iommus = <&iommu 0>;
143 #size-cells = <0>;
158 reg = <0x01c0e000 0x2000>;
171 reg = <0x01800000 0x4000>;
184 reg = <0x01904000 0x1000>;
194 reg = <0x03000000 0x1000>;
201 reg = <0x00028000 0x1e000>;
204 ranges = <0 0x00028000 0x1e000>;
206 de2_sram: sram-section@0 {
209 reg = <0x0000 0x1e000>;
215 reg = <0x01a00000 0x200000>;
218 ranges = <0 0x01a00000 0x200000>;
220 ve_sram: sram-section@0 {
223 reg = <0x000000 0x200000>;
230 reg = <0x03001000 0x1000>;
231 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
239 reg = <0x03002000 0x1000>;
252 reg = <0x03003000 0x1000>;
261 reg = <0x03006000 0x400>;
266 reg = <0x14 0x8>;
270 reg = <0x1c 0x4>;
277 reg = <0x030090a0 0x20>;
286 reg = <0x0300a000 0x400>;
296 reg = <0x0300b000 0x400>;
301 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
410 reg = <0x03021000 0x1000>,
411 <0x03022000 0x2000>,
412 <0x03024000 0x2000>,
413 <0x03026000 0x2000>;
421 reg = <0x030f0000 0x10000>;
431 reg = <0x04020000 0x1000>;
438 pinctrl-0 = <&mmc0_pins>;
442 #size-cells = <0>;
448 reg = <0x04021000 0x1000>;
455 pinctrl-0 = <&mmc1_pins>;
459 #size-cells = <0>;
465 reg = <0x04022000 0x1000>;
472 pinctrl-0 = <&mmc2_pins>;
476 #size-cells = <0>;
481 reg = <0x05000000 0x400>;
482 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
492 reg = <0x05000400 0x400>;
503 reg = <0x05000800 0x400>;
514 reg = <0x05000c00 0x400>;
526 reg = <0x05002000 0x400>;
531 pinctrl-0 = <&i2c0_pins>;
534 #size-cells = <0>;
540 reg = <0x05002400 0x400>;
545 pinctrl-0 = <&i2c1_pins>;
548 #size-cells = <0>;
554 reg = <0x05002800 0x400>;
559 pinctrl-0 = <&i2c2_pins>;
562 #size-cells = <0>;
568 reg = <0x05010000 0x1000>;
577 #size-cells = <0>;
583 reg = <0x05011000 0x1000>;
592 #size-cells = <0>;
599 reg = <0x05020000 0x10000>;
611 #size-cells = <0>;
616 #sound-dai-cells = <0>;
618 reg = <0x05093000 0x400>;
626 pinctrl-0 = <&spdif_tx_pin>;
633 reg = <0x05100000 0x0400>;
638 phys = <&usb2phy 0>;
640 extcon = <&usb2phy 0>;
646 reg = <0x05100400 0x24>,
647 <0x05101800 0x4>,
648 <0x05311800 0x4>;
666 reg = <0x05101000 0x100>;
673 phys = <&usb2phy 0>;
680 reg = <0x05101400 0x100>;
685 phys = <&usb2phy 0>;
692 reg = <0x05200000 0x10000>;
696 <&rtc 0>;
715 reg = <0x5210000 0x10000>;
718 #phy-cells = <0>;
724 reg = <0x05311000 0x100>;
738 reg = <0x05311400 0x100>;
750 reg = <0x06000000 0x10000>;
763 pinctrl-0 = <&hdmi_pins>;
768 #size-cells = <0>;
770 hdmi_in: port@0 {
771 reg = <0>;
786 reg = <0x06010000 0x10000>;
791 #phy-cells = <0>;
796 reg = <0x06510000 0x1000>;
807 #size-cells = <0>;
809 tcon_top_mixer0_in: port@0 {
811 #size-cells = <0>;
812 reg = <0>;
814 tcon_top_mixer0_in_mixer0: endpoint@0 {
815 reg = <0>;
822 #size-cells = <0>;
833 #size-cells = <0>;
836 tcon_top_hdmi_in_tcon_tv: endpoint@0 {
837 reg = <0>;
855 reg = <0x06515000 0x1000>;
866 #size-cells = <0>;
868 tcon_tv_in: port@0 {
869 reg = <0>;
878 #size-cells = <0>;
891 reg = <0x07000000 0x400>;
900 reg = <0x07010000 0x400>;
901 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
911 reg = <0x07020400 0x20>;
921 reg = <0x07021000 0x400>;
927 reg = <0x07022000 0x400>;
930 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
951 reg = <0x07040000 0x400>;
958 pinctrl-0 = <&r_ir_rx_pin>;
965 reg = <0x07081400 0x400>;
970 pinctrl-0 = <&r_i2c_pins>;
973 #size-cells = <0>;
978 reg = <0x05070400 0x100>;
991 polling-delay-passive = <0>;
992 polling-delay = <0>;
993 thermal-sensors = <&ths 0>;
1004 hysteresis = <0>;
1021 polling-delay-passive = <0>;
1022 polling-delay = <0>;