Lines Matching +full:0 +full:x1000
136 #size-cells = <0>;
158 cpu0: cpu@0 {
161 reg = <0x000>;
176 reg = <0x001>;
191 reg = <0x100>;
206 reg = <0x101>;
221 CPU_SLEEP_0: cpu-sleep-0 {
227 arm,psci-suspend-param = <0x0010000>;
249 cpu_suspend = <0x84000001>;
250 cpu_off = <0x84000002>;
251 cpu_on = <0x84000003>;
256 #clock-cells = <0>;
263 #clock-cells = <0>;
270 #clock-cells = <0>;
271 clock-frequency = <0>;
330 reg = <0 0xb7000000 0 0x500000>;
331 alignment = <0x1000>;
358 reg = <0 0x10000000 0 0x1000>;
364 reg = <0 0x10001000 0 0x1000>;
371 reg = <0 0x10003000 0 0x1000>;
378 reg = <0 0x10005000 0 0x1000>;
383 reg = <0 0x1000b000 0 0x1000>;
456 reg = <0 0x10006000 0 0x1000>;
468 reg = <0 0x10007000 0 0x100>;
474 reg = <0 0x10008000 0 0x1000>;
482 reg = <0 0x1000d000 0 0x1000>;
493 reg = <0 0x10013000 0 0xbc>;
501 reg = <0 0x10020000 0 0x30000>,
502 <0 0x10050000 0 0x100>;
516 reg = <0 0x10200620 0 0x20>;
521 reg = <0 0x10205000 0 0x1000>;
532 reg = <0 0x10206000 0 0x1000>;
536 reg = <0x528 0xc>;
542 reg = <0 0x10209000 0 0x1000>;
548 reg = <0 0x10209100 0 0x24>;
552 mediatek,ibias = <0xa>;
553 mediatek,ibias_up = <0x1c>;
554 #clock-cells = <0>;
555 #phy-cells = <0>;
561 reg = <0 0x10212000 0 0x1000>;
570 reg = <0 0x10215000 0 0x1000>;
573 #clock-cells = <0>;
574 #phy-cells = <0>;
580 reg = <0 0x10216000 0 0x1000>;
583 #clock-cells = <0>;
584 #phy-cells = <0>;
593 reg = <0 0x10221000 0 0x1000>,
594 <0 0x10222000 0 0x2000>,
595 <0 0x10224000 0 0x2000>,
596 <0 0x10226000 0 0x2000>;
603 reg = <0 0x11001000 0 0x1000>;
612 reg = <0 0x11002000 0 0x400>;
622 reg = <0 0x11003000 0 0x400>;
632 reg = <0 0x11004000 0 0x400>;
642 reg = <0 0x11005000 0 0x400>;
651 reg = <0 0x11007000 0 0x70>,
652 <0 0x11000100 0 0x80>;
659 pinctrl-0 = <&i2c0_pins_a>;
661 #size-cells = <0>;
667 reg = <0 0x11008000 0 0x70>,
668 <0 0x11000180 0 0x80>;
675 pinctrl-0 = <&i2c1_pins_a>;
677 #size-cells = <0>;
683 reg = <0 0x11009000 0 0x70>,
684 <0 0x11000200 0 0x80>;
691 pinctrl-0 = <&i2c2_pins_a>;
693 #size-cells = <0>;
700 #size-cells = <0>;
701 reg = <0 0x1100a000 0 0x1000>;
711 #thermal-sensor-cells = <0>;
713 reg = <0 0x1100b000 0 0x1000>;
714 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
726 reg = <0 0x1100d000 0 0xe0>;
731 #size-cells = <0>;
737 reg = <0 0x11010000 0 0x70>,
738 <0 0x11000280 0 0x80>;
745 pinctrl-0 = <&i2c3_pins_a>;
747 #size-cells = <0>;
753 reg = <0 0x11011000 0 0x70>,
754 <0 0x11000300 0 0x80>;
761 pinctrl-0 = <&i2c4_pins_a>;
763 #size-cells = <0>;
770 reg = <0 0x11012000 0 0x1C>;
777 reg = <0 0x11013000 0 0x70>,
778 <0 0x11000080 0 0x80>;
785 pinctrl-0 = <&i2c6_pins_a>;
787 #size-cells = <0>;
793 reg = <0 0x11220000 0 0x1000>;
824 reg = <0 0x11230000 0 0x1000>;
834 reg = <0 0x11240000 0 0x1000>;
844 reg = <0 0x11250000 0 0x1000>;
854 reg = <0 0x11260000 0 0x1000>;
864 reg = <0 0x11271000 0 0x3000>,
865 <0 0x11280700 0 0x0100>;
874 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
882 reg = <0 0x11270000 0 0x1000>;
894 reg = <0 0x11290000 0 0x800>;
901 reg = <0 0x11290800 0 0x100>;
909 reg = <0 0x11290900 0 0x700>;
917 reg = <0 0x11291000 0 0x100>;
927 reg = <0 0x14000000 0 0x1000>;
932 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
934 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
940 reg = <0 0x14001000 0 0x1000>;
951 reg = <0 0x14002000 0 0x1000>;
961 reg = <0 0x14003000 0 0x1000>;
968 reg = <0 0x14004000 0 0x1000>;
975 reg = <0 0x14005000 0 0x1000>;
982 reg = <0 0x14006000 0 0x1000>;
991 reg = <0 0x14007000 0 0x1000>;
1000 reg = <0 0x14008000 0 0x1000>;
1009 reg = <0 0x1400c000 0 0x1000>;
1015 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1020 reg = <0 0x1400d000 0 0x1000>;
1026 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1031 reg = <0 0x1400e000 0 0x1000>;
1037 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1042 reg = <0 0x1400f000 0 0x1000>;
1048 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1053 reg = <0 0x14010000 0 0x1000>;
1059 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1064 reg = <0 0x14011000 0 0x1000>;
1070 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1075 reg = <0 0x14012000 0 0x1000>;
1081 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1086 reg = <0 0x14013000 0 0x1000>;
1090 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1095 reg = <0 0x14014000 0 0x1000>;
1099 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1104 reg = <0 0x14015000 0 0x1000>;
1108 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1113 reg = <0 0x14016000 0 0x1000>;
1117 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1122 reg = <0 0x14017000 0 0x1000>;
1129 reg = <0 0x14018000 0 0x1000>;
1136 reg = <0 0x14019000 0 0x1000>;
1143 reg = <0 0x1401a000 0 0x1000>;
1151 reg = <0 0x1401b000 0 0x1000>;
1165 reg = <0 0x1401c000 0 0x1000>;
1179 reg = <0 0x1401d000 0 0x1000>;
1198 reg = <0 0x1401e000 0 0x1000>;
1209 reg = <0 0x1401f000 0 0x1000>;
1219 reg = <0 0x14020000 0 0x1000>;
1229 reg = <0 0x14021000 0 0x1000>;
1239 reg = <0 0x14022000 0 0x1000>;
1248 reg = <0 0x14023000 0 0x1000>;
1254 reg = <0 0x14025000 0 0x400>;
1262 pinctrl-0 = <&hdmi_pin>;
1265 mediatek,syscon-hdmi = <&mmsys 0x900>;
1272 #size-cells = <0>;
1274 port@0 {
1275 reg = <0>;
1286 reg = <0 0x14027000 0 0x1000>;
1296 reg = <0 0x15000000 0 0x1000>;
1302 reg = <0 0x15001000 0 0x1000>;
1312 reg = <0 0x16000000 0 0x1000>;
1318 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
1319 <0 0x16020000 0 0x1000>, /* VDEC_MISC */
1320 <0 0x16021000 0 0x800>, /* VDEC_LD */
1321 <0 0x16021800 0 0x800>, /* VDEC_TOP */
1322 <0 0x16022000 0 0x1000>, /* VDEC_CM */
1323 <0 0x16023000 0 0x1000>, /* VDEC_AD */
1324 <0 0x16024000 0 0x1000>, /* VDEC_AV */
1325 <0 0x16025000 0 0x1000>, /* VDEC_PP */
1326 <0 0x16026800 0 0x800>, /* VDEC_HWD */
1327 <0 0x16027000 0 0x800>, /* VDEC_HWQ */
1328 <0 0x16027800 0 0x800>, /* VDEC_HWB */
1329 <0 0x16028400 0 0x400>; /* VDEC_HWG */
1366 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1371 reg = <0 0x16010000 0 0x1000>;
1381 reg = <0 0x18000000 0 0x1000>;
1387 reg = <0 0x18001000 0 0x1000>;
1397 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
1398 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
1440 reg = <0 0x18004000 0 0x1000>;
1454 reg = <0 0x19000000 0 0x1000>;
1460 reg = <0 0x19001000 0 0x1000>;