Lines Matching +full:0 +full:xd00000

17 			#clock-cells = <0>;
23 			#clock-cells = <0>;
28 		#address-cells = <0x1>;
29 		#size-cells = <0x0>;
31 		CPU0: cpu@0 {
34 			reg = <0x0>;
43 			reg = <0x1>;
51 			reg = <0x2>;
59 			reg = <0x3>;
65 			cache-level = <0x2>;
80 		#address-cells = <0x1>;
81 		#size-cells = <0x1>;
82 		ranges = <0 0 0 0xffffffff>;
87 			reg = <0x00058000 0x1c4>;
104 				reg = <0x00058200 0x130>,       /* Tx */
105 				      <0x00058400 0x200>,     /* Rx */
106 				      <0x00058800 0x1f8>,     /* PCS  */
107 				      <0x00058600 0x044>;     /* PCS misc*/
108 				#phy-cells = <0>;
117 			reg = <0x00059000 0x180>;
118 			#phy-cells = <0>;
130 			reg = <0x00078000 0x1c4>;
147 				reg = <0x00078200 0x130>,       /* Tx */
148 				      <0x00078400 0x200>,     /* Rx */
149 				      <0x00078800 0x1f8>,     /* PCS  */
150 				      <0x00078600 0x044>;     /* PCS misc*/
151 				#phy-cells = <0>;
160 			reg = <0x00079000 0x180>;
161 			#phy-cells = <0>;
172 			reg = <0x00086000 0x1000>;
173 			#phy-cells = <0>;
187 			reg = <0x0008e000 0x1000>;
188 			#phy-cells = <0>;
202 			reg = <0x01000000 0x300000>;
205 			gpio-ranges = <&tlmm 0 0 70>;
206 			#gpio-cells = <0x2>;
208 			#interrupt-cells = <0x2>;
217 			i2c_0_pins: i2c-0-pinmux {
224 			spi_0_pins: spi-0-pins {
252 			reg = <0x01800000 0x80000>;
253 			#clock-cells = <0x1>;
254 			#reset-cells = <0x1>;
259 			reg = <0x7824900 0x500>, <0x7824000 0x800>;
281 			reg = <0x07884000 0x2b000>;
286 			qcom,ee = <0>;
291 			reg = <0x078af000 0x200>;
301 			reg = <0x078b1000 0x200>;
309 			pinctrl-0 = <&hsuart_pins>;
316 			reg = <0x078b3000 0x200>;
321 			pinctrl-0 = <&serial_4_pins>;
329 			#size-cells = <0>;
330 			reg = <0x078b5000 0x600>;
338 			pinctrl-0 = <&spi_0_pins>;
346 			#size-cells = <0>;
347 			reg = <0x078b6000 0x600>;
355 			pinctrl-0 = <&i2c_0_pins>;
363 			#size-cells = <0>;
364 			reg = <0x078b7000 0x600>;
377 			reg = <0x07984000 0x1a000>;
382 			qcom,ee = <0>;
388 			reg = <0x079b0000 0x10000>;
390 			#size-cells = <0>;
395 			dmas = <&qpic_bam 0>,
399 			pinctrl-0 = <&qpic_pins>;
406 			reg = <0x08af8800 0x400>;
432 				reg = <0x8a00000 0xcd00>;
438 				snps,hird-threshold = /bits/ 8 <0x0>;
447 			reg = <0x08cf8800 0x400>;
473 				reg = <0x8c00000 0xcd00>;
479 				snps,hird-threshold = /bits/ 8 <0x0>;
489 			#interrupt-cells = <0x3>;
490 			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
503 			reg = <0xb017000 0x1000>;
514 			reg = <0x0b120000 0x1000>;
518 				frame-number = <0>;
521 				reg = <0x0b121000 0x1000>,
522 				      <0x0b122000 0x1000>;
528 				reg = <0x0b123000 0x1000>;
535 				reg = <0x0b124000 0x1000>;
542 				reg = <0x0b125000 0x1000>;
549 				reg = <0x0b126000 0x1000>;
556 				reg = <0x0b127000 0x1000>;
563 				reg = <0x0b128000 0x1000>;
570 			reg =  <0x10000000 0xf1d>,
571 			       <0x10000f20 0xa8>,
572 			       <0x00088000 0x2000>,
573 			       <0x10100000 0x1000>;
577 			bus-range = <0x00 0xff>;
585 			ranges = <0x81000000 0 0x10200000 0x10200000
586 				  0 0x100000   /* downstream I/O */
587 				  0x82000000 0 0x10300000 0x10300000
588 				  0 0xd00000>; /* non-prefetchable memory */
593 			interrupt-map-mask = <0 0 0 0x7>;
594 			interrupt-map = <0 0 0 1 &intc 0 142
596 					<0 0 0 2 &intc 0 143
598 					<0 0 0 3 &intc 0 144
600 					<0 0 0 4 &intc 0 145
632 			reg = <0x20000000 0xf1d>,
633 			      <0x20000f20 0xa8>,
634 			      <0x00080000 0x2000>,
635 			      <0x20100000 0x1000>;
638 			linux,pci-domain = <0>;
639 			bus-range = <0x00 0xff>;
647 			ranges = <0x81000000 0 0x20200000 0x20200000
648 				  0 0x100000   /* downstream I/O */
649 				  0x82000000 0 0x20300000 0x20300000
650 				  0 0xd00000>; /* non-prefetchable memory */
655 			interrupt-map-mask = <0 0 0 0x7>;
656 			interrupt-map = <0 0 0 1 &intc 0 75
658 					<0 0 0 2 &intc 0 78
660 					<0 0 0 3 &intc 0 79
662 					<0 0 0 4 &intc 0 83