Lines Matching full:mmcc
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
483 mmcc: clock-controller@8c0000 { label
484 compatible = "qcom,mmcc-msm8996";
489 assigned-clocks = <&mmcc MMPLL9_PLL>,
490 <&mmcc MMPLL1_PLL>,
491 <&mmcc MMPLL3_PLL>,
492 <&mmcc MMPLL4_PLL>,
493 <&mmcc MMPLL5_PLL>;
511 power-domains = <&mmcc MDSS_GDSC>;
517 clocks = <&mmcc MDSS_AHB_CLK>;
532 clocks = <&mmcc MDSS_AHB_CLK>,
533 <&mmcc MDSS_AXI_CLK>,
534 <&mmcc MDSS_MDP_CLK>,
535 <&mmcc SMMU_MDP_AXI_CLK>,
536 <&mmcc MDSS_VSYNC_CLK>;
570 clocks = <&mmcc MDSS_MDP_CLK>,
571 <&mmcc MDSS_AHB_CLK>,
572 <&mmcc MDSS_HDMI_CLK>,
573 <&mmcc MDSS_HDMI_AHB_CLK>,
574 <&mmcc MDSS_EXTPCLK_CLK>;
615 clocks = <&mmcc MDSS_AHB_CLK>,
630 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
631 <&mmcc GPU_AHB_CLK>,
632 <&mmcc GPU_GX_RBBMTIMER_CLK>,
642 power-domains = <&mmcc GPU_GX_GDSC>;
1009 power-domains = <&mmcc VFE0_GDSC>,
1010 <&mmcc VFE1_GDSC>;
1011 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1012 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1013 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1014 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1015 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1016 <&mmcc CAMSS_CSI0_AHB_CLK>,
1017 <&mmcc CAMSS_CSI0_CLK>,
1018 <&mmcc CAMSS_CSI0PHY_CLK>,
1019 <&mmcc CAMSS_CSI0PIX_CLK>,
1020 <&mmcc CAMSS_CSI0RDI_CLK>,
1021 <&mmcc CAMSS_CSI1_AHB_CLK>,
1022 <&mmcc CAMSS_CSI1_CLK>,
1023 <&mmcc CAMSS_CSI1PHY_CLK>,
1024 <&mmcc CAMSS_CSI1PIX_CLK>,
1025 <&mmcc CAMSS_CSI1RDI_CLK>,
1026 <&mmcc CAMSS_CSI2_AHB_CLK>,
1027 <&mmcc CAMSS_CSI2_CLK>,
1028 <&mmcc CAMSS_CSI2PHY_CLK>,
1029 <&mmcc CAMSS_CSI2PIX_CLK>,
1030 <&mmcc CAMSS_CSI2RDI_CLK>,
1031 <&mmcc CAMSS_CSI3_AHB_CLK>,
1032 <&mmcc CAMSS_CSI3_CLK>,
1033 <&mmcc CAMSS_CSI3PHY_CLK>,
1034 <&mmcc CAMSS_CSI3PIX_CLK>,
1035 <&mmcc CAMSS_CSI3RDI_CLK>,
1036 <&mmcc CAMSS_AHB_CLK>,
1037 <&mmcc CAMSS_VFE0_CLK>,
1038 <&mmcc CAMSS_CSI_VFE0_CLK>,
1039 <&mmcc CAMSS_VFE0_AHB_CLK>,
1040 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1041 <&mmcc CAMSS_VFE1_CLK>,
1042 <&mmcc CAMSS_CSI_VFE1_CLK>,
1043 <&mmcc CAMSS_VFE1_AHB_CLK>,
1044 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1045 <&mmcc CAMSS_VFE_AHB_CLK>,
1046 <&mmcc CAMSS_VFE_AXI_CLK>;
1100 power-domains = <&mmcc CAMSS_GDSC>;
1101 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1102 <&mmcc CAMSS_CCI_AHB_CLK>,
1103 <&mmcc CAMSS_CCI_CLK>,
1104 <&mmcc CAMSS_AHB_CLK>;
1109 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1110 <&mmcc CAMSS_CCI_CLK>;
1141 clocks = <&mmcc GPU_AHB_CLK>,
1145 power-domains = <&mmcc GPU_GDSC>;
1152 power-domains = <&mmcc VENUS_GDSC>;
1153 clocks = <&mmcc VIDEO_CORE_CLK>,
1154 <&mmcc VIDEO_AHB_CLK>,
1155 <&mmcc VIDEO_AXI_CLK>,
1156 <&mmcc VIDEO_MAXI_CLK>;
1183 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
1185 power-domains = <&mmcc VENUS_CORE0_GDSC>;
1190 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
1192 power-domains = <&mmcc VENUS_CORE1_GDSC>;
1205 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
1206 <&mmcc SMMU_MDP_AXI_CLK>;
1209 power-domains = <&mmcc MDSS_GDSC>;
1224 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
1225 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
1226 <&mmcc SMMU_VIDEO_AXI_CLK>;
1240 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
1241 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
1242 <&mmcc SMMU_VFE_AXI_CLK>;