Lines Matching +full:0 +full:xe6150000
21 * The external audio clocks are configured as 0 Hz fixed frequency
27 #clock-cells = <0>;
28 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
39 #clock-cells = <0>;
40 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
74 #size-cells = <0>;
76 a57_0: cpu@0 {
78 reg = <0x0>;
91 reg = <0x1>;
100 L2_CA57: cache-controller-0 {
110 #clock-cells = <0>;
112 clock-frequency = <0>;
117 #clock-cells = <0>;
119 clock-frequency = <0>;
125 #clock-cells = <0>;
126 clock-frequency = <0>;
144 #clock-cells = <0>;
145 clock-frequency = <0>;
158 reg = <0 0xe6020000 0 0x0c>;
168 reg = <0 0xe6050000 0 0x50>;
172 gpio-ranges = <&pfc 0 0 16>;
183 reg = <0 0xe6051000 0 0x50>;
187 gpio-ranges = <&pfc 0 32 29>;
198 reg = <0 0xe6052000 0 0x50>;
202 gpio-ranges = <&pfc 0 64 15>;
213 reg = <0 0xe6053000 0 0x50>;
217 gpio-ranges = <&pfc 0 96 16>;
228 reg = <0 0xe6054000 0 0x50>;
232 gpio-ranges = <&pfc 0 128 18>;
243 reg = <0 0xe6055000 0 0x50>;
247 gpio-ranges = <&pfc 0 160 26>;
258 reg = <0 0xe6055400 0 0x50>;
262 gpio-ranges = <&pfc 0 192 32>;
273 reg = <0 0xe6055800 0 0x50>;
277 gpio-ranges = <&pfc 0 224 4>;
287 reg = <0 0xe6060000 0 0x50c>;
293 reg = <0 0xe60f0000 0 0x1004>;
306 reg = <0 0xe6130000 0 0x1004>;
325 reg = <0 0xe6140000 0 0x1004>;
344 reg = <0 0xe6148000 0 0x1004>;
362 reg = <0 0xe6150000 0 0x1000>;
366 #power-domain-cells = <0>;
372 reg = <0 0xe6160000 0 0x0200>;
377 reg = <0 0xe6180000 0 0x0400>;
383 reg = <0 0xe6198000 0 0x100>,
384 <0 0xe61a0000 0 0x100>,
385 <0 0xe61a8000 0 0x100>;
399 reg = <0 0xe61c0000 0 0x200>;
400 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
413 reg = <0 0xe61e0000 0 0x30>;
426 reg = <0 0xe6fc0000 0 0x30>;
439 reg = <0 0xe6fd0000 0 0x30>;
452 reg = <0 0xe6fe0000 0 0x30>;
465 reg = <0 0xffc00000 0 0x30>;
478 #size-cells = <0>;
481 reg = <0 0xe6500000 0 0x40>;
486 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
487 <&dmac2 0x91>, <&dmac2 0x90>;
495 #size-cells = <0>;
498 reg = <0 0xe6508000 0 0x40>;
503 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
504 <&dmac2 0x93>, <&dmac2 0x92>;
512 #size-cells = <0>;
515 reg = <0 0xe6510000 0 0x40>;
520 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
521 <&dmac2 0x95>, <&dmac2 0x94>;
529 #size-cells = <0>;
532 reg = <0 0xe66d0000 0 0x40>;
537 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
545 #size-cells = <0>;
548 reg = <0 0xe66d8000 0 0x40>;
553 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
561 #size-cells = <0>;
564 reg = <0 0xe66e0000 0 0x40>;
569 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
577 #size-cells = <0>;
580 reg = <0 0xe66e8000 0 0x40>;
585 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
593 #size-cells = <0>;
597 reg = <0 0xe60b0000 0 0x425>;
602 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
611 reg = <0 0xe6540000 0 0x60>;
617 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
618 <&dmac2 0x31>, <&dmac2 0x30>;
629 reg = <0 0xe6550000 0 0x60>;
635 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
636 <&dmac2 0x33>, <&dmac2 0x32>;
647 reg = <0 0xe6560000 0 0x60>;
653 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
654 <&dmac2 0x35>, <&dmac2 0x34>;
665 reg = <0 0xe66a0000 0 0x60>;
671 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
682 reg = <0 0xe66b0000 0 0x60>;
688 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
698 reg = <0 0xe6590000 0 0x200>;
701 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
702 <&usb_dmac1 0>, <&usb_dmac1 1>;
715 reg = <0 0xe6590630 0 0x02>;
720 #clock-cells = <0>;
730 reg = <0 0xe65a0000 0 0x100>;
744 reg = <0 0xe65b0000 0 0x100>;
758 reg = <0 0xe65ee000 0 0x90>;
764 #phy-cells = <0>;
771 reg = <0 0xe6700000 0 0x10000>;
800 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
813 reg = <0 0xe7300000 0 0x10000>;
842 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
855 reg = <0 0xe7310000 0 0x10000>;
896 reg = <0 0xe6740000 0 0x1000>;
897 renesas,ipmmu-main = <&ipmmu_mm 0>;
904 reg = <0 0xe7740000 0 0x1000>;
912 reg = <0 0xe6570000 0 0x1000>;
920 reg = <0 0xe67b0000 0 0x1000>;
929 reg = <0 0xec670000 0 0x1000>;
937 reg = <0 0xfd800000 0 0x1000>;
945 reg = <0 0xfe6b0000 0 0x1000>;
953 reg = <0 0xfebd0000 0 0x1000>;
961 reg = <0 0xfe990000 0 0x1000>;
970 reg = <0 0xe6800000 0 0x800>;
1007 rx-internal-delay-ps = <0>;
1008 tx-internal-delay-ps = <0>;
1011 #size-cells = <0>;
1018 reg = <0 0xe6c30000 0 0x1000>;
1034 reg = <0 0xe6c38000 0 0x1000>;
1050 reg = <0 0xe66c0000 0 0x8000>;
1074 reg = <0 0xe6e30000 0 0x8>;
1084 reg = <0 0xe6e31000 0 0x8>;
1094 reg = <0 0xe6e32000 0 0x8>;
1104 reg = <0 0xe6e33000 0 0x8>;
1114 reg = <0 0xe6e34000 0 0x8>;
1124 reg = <0 0xe6e35000 0 0x8>;
1134 reg = <0 0xe6e36000 0 0x8>;
1145 reg = <0 0xe6e60000 0 0x40>;
1151 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1152 <&dmac2 0x51>, <&dmac2 0x50>;
1162 reg = <0 0xe6e68000 0 0x40>;
1168 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1169 <&dmac2 0x53>, <&dmac2 0x52>;
1179 reg = <0 0xe6e88000 0 0x40>;
1185 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1186 <&dmac2 0x13>, <&dmac2 0x12>;
1196 reg = <0 0xe6c50000 0 0x40>;
1202 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1212 reg = <0 0xe6c40000 0 0x40>;
1218 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1228 reg = <0 0xe6f30000 0 0x40>;
1234 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1235 <&dmac2 0x5b>, <&dmac2 0x5a>;
1245 reg = <0 0xe6e90000 0 0x0064>;
1248 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1249 <&dmac2 0x41>, <&dmac2 0x40>;
1254 #size-cells = <0>;
1261 reg = <0 0xe6ea0000 0 0x0064>;
1264 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1265 <&dmac2 0x43>, <&dmac2 0x42>;
1270 #size-cells = <0>;
1277 reg = <0 0xe6c00000 0 0x0064>;
1280 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1285 #size-cells = <0>;
1292 reg = <0 0xe6c10000 0 0x0064>;
1295 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1300 #size-cells = <0>;
1306 reg = <0 0xe6ef0000 0 0x1000>;
1311 renesas,id = <0>;
1316 #size-cells = <0>;
1320 #size-cells = <0>;
1324 vin0csi20: endpoint@0 {
1325 reg = <0>;
1338 reg = <0 0xe6ef1000 0 0x1000>;
1348 #size-cells = <0>;
1352 #size-cells = <0>;
1356 vin1csi20: endpoint@0 {
1357 reg = <0>;
1370 reg = <0 0xe6ef2000 0 0x1000>;
1380 #size-cells = <0>;
1384 #size-cells = <0>;
1388 vin2csi20: endpoint@0 {
1389 reg = <0>;
1402 reg = <0 0xe6ef3000 0 0x1000>;
1412 #size-cells = <0>;
1416 #size-cells = <0>;
1420 vin3csi20: endpoint@0 {
1421 reg = <0>;
1434 reg = <0 0xe6ef4000 0 0x1000>;
1444 #size-cells = <0>;
1448 #size-cells = <0>;
1452 vin4csi20: endpoint@0 {
1453 reg = <0>;
1466 reg = <0 0xe6ef5000 0 0x1000>;
1476 #size-cells = <0>;
1480 #size-cells = <0>;
1484 vin5csi20: endpoint@0 {
1485 reg = <0>;
1498 reg = <0 0xe6ef6000 0 0x1000>;
1508 #size-cells = <0>;
1512 #size-cells = <0>;
1516 vin6csi20: endpoint@0 {
1517 reg = <0>;
1530 reg = <0 0xe6ef7000 0 0x1000>;
1540 #size-cells = <0>;
1544 #size-cells = <0>;
1548 vin7csi20: endpoint@0 {
1549 reg = <0>;
1564 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1570 * clkout : #clock-cells = <0>; <&rcar_sound>;
1574 reg = <0 0xec500000 0 0x1000>, /* SCU */
1575 <0 0xec5a0000 0 0x100>, /* ADG */
1576 <0 0xec540000 0 0x1000>, /* SSIU */
1577 <0 0xec541000 0 0x280>, /* SSI */
1578 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1601 "ssi.1", "ssi.0",
1604 "src.1", "src.0",
1605 "mix.1", "mix.0",
1606 "ctu.1", "ctu.0",
1607 "dvc.0", "dvc.1",
1619 "ssi.1", "ssi.0";
1623 ctu00: ctu-0 { };
1634 dvc0: dvc-0 {
1635 dmas = <&audma1 0xbc>;
1639 dmas = <&audma1 0xbe>;
1645 mix0: mix-0 { };
1650 src0: src-0 {
1652 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1657 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1662 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1667 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1672 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1677 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1682 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1687 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1692 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1697 dmas = <&audma0 0x97>, <&audma1 0xba>;
1703 ssi0: ssi-0 {
1705 dmas = <&audma0 0x01>, <&audma1 0x02>;
1710 dmas = <&audma0 0x03>, <&audma1 0x04>;
1715 dmas = <&audma0 0x05>, <&audma1 0x06>;
1720 dmas = <&audma0 0x07>, <&audma1 0x08>;
1725 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1730 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1735 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1740 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1745 dmas = <&audma0 0x11>, <&audma1 0x12>;
1750 dmas = <&audma0 0x13>, <&audma1 0x14>;
1756 ssiu00: ssiu-0 {
1757 dmas = <&audma0 0x15>, <&audma1 0x16>;
1761 dmas = <&audma0 0x35>, <&audma1 0x36>;
1765 dmas = <&audma0 0x37>, <&audma1 0x38>;
1769 dmas = <&audma0 0x47>, <&audma1 0x48>;
1773 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1777 dmas = <&audma0 0x43>, <&audma1 0x44>;
1781 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1785 dmas = <&audma0 0x53>, <&audma1 0x54>;
1789 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1793 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1797 dmas = <&audma0 0x57>, <&audma1 0x58>;
1801 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1805 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1809 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1813 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1817 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1821 dmas = <&audma0 0x63>, <&audma1 0x64>;
1825 dmas = <&audma0 0x67>, <&audma1 0x68>;
1829 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1833 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1837 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1841 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1845 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1849 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1853 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1857 dmas = <&audma0 0x21>, <&audma1 0x22>;
1861 dmas = <&audma0 0x23>, <&audma1 0x24>;
1865 dmas = <&audma0 0x25>, <&audma1 0x26>;
1869 dmas = <&audma0 0x27>, <&audma1 0x28>;
1873 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1877 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1881 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
1885 dmas = <&audma0 0x71>, <&audma1 0x72>;
1889 dmas = <&audma0 0x17>, <&audma1 0x18>;
1893 dmas = <&audma0 0x19>, <&audma1 0x1A>;
1897 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
1901 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
1905 dmas = <&audma0 0x1F>, <&audma1 0x20>;
1909 dmas = <&audma0 0x31>, <&audma1 0x32>;
1913 dmas = <&audma0 0x33>, <&audma1 0x34>;
1917 dmas = <&audma0 0x73>, <&audma1 0x74>;
1921 dmas = <&audma0 0x75>, <&audma1 0x76>;
1925 dmas = <&audma0 0x79>, <&audma1 0x7a>;
1929 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
1933 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
1937 dmas = <&audma0 0x7F>, <&audma1 0x80>;
1941 dmas = <&audma0 0x81>, <&audma1 0x82>;
1945 dmas = <&audma0 0x83>, <&audma1 0x84>;
1949 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
1953 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
1957 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
1961 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
1970 reg = <0 0xec700000 0 0x10000>;
2004 reg = <0 0xec720000 0 0x10000>;
2038 reg = <0 0xee000000 0 0xc00>;
2049 reg = <0 0xee020000 0 0x400>;
2059 reg = <0 0xee080000 0 0x100>;
2071 reg = <0 0xee0a0000 0 0x100>;
2083 reg = <0 0xee080100 0 0x100>;
2096 reg = <0 0xee0a0100 0 0x100>;
2110 reg = <0 0xee080200 0 0x700>;
2122 reg = <0 0xee0a0200 0 0x700>;
2133 reg = <0 0xee100000 0 0x2000>;
2145 reg = <0 0xee120000 0 0x2000>;
2157 reg = <0 0xee140000 0 0x2000>;
2169 reg = <0 0xee160000 0 0x2000>;
2181 reg = <0 0xee300000 0 0x200000>;
2192 #address-cells = <0>;
2194 reg = <0x0 0xf1010000 0 0x1000>,
2195 <0x0 0xf1020000 0 0x20000>,
2196 <0x0 0xf1040000 0 0x20000>,
2197 <0x0 0xf1060000 0 0x20000>;
2209 reg = <0 0xfe000000 0 0x80000>;
2212 bus-range = <0x00 0xff>;
2214 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2215 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2216 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2217 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2219 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2224 interrupt-map-mask = <0 0 0 0>;
2225 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2236 reg = <0 0xee800000 0 0x80000>;
2239 bus-range = <0x00 0xff>;
2241 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2242 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2243 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2244 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2246 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2251 interrupt-map-mask = <0 0 0 0>;
2252 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2263 reg = <0x0 0xfe000000 0 0x80000>,
2264 <0x0 0xfe100000 0 0x100000>,
2265 <0x0 0xfe200000 0 0x200000>,
2266 <0x0 0x30000000 0 0x8000000>,
2267 <0x0 0x38000000 0 0x8000000>;
2282 reg = <0x0 0xee800000 0 0x80000>,
2283 <0x0 0xee900000 0 0x100000>,
2284 <0x0 0xeea00000 0 0x200000>,
2285 <0x0 0xc0000000 0 0x8000000>,
2286 <0x0 0xc8000000 0 0x8000000>;
2300 reg = <0 0xfe940000 0 0x2400>;
2310 reg = <0 0xfe950000 0 0x200>;
2318 reg = <0 0xfe960000 0 0x8000>;
2329 reg = <0 0xfe9a0000 0 0x8000>;
2340 reg = <0 0xfea20000 0 0x5000>;
2351 reg = <0 0xfea28000 0 0x5000>;
2362 reg = <0 0xfe96f000 0 0x200>;
2370 reg = <0 0xfea27000 0 0x200>;
2378 reg = <0 0xfea2f000 0 0x200>;
2386 reg = <0 0xfe9af000 0 0x200>;
2394 reg = <0 0xfea80000 0 0x10000>;
2403 #size-cells = <0>;
2407 #size-cells = <0>;
2411 csi20vin0: endpoint@0 {
2412 reg = <0>;
2449 reg = <0 0xfeaa0000 0 0x10000>;
2458 #size-cells = <0>;
2462 #size-cells = <0>;
2466 csi40vin0: endpoint@0 {
2467 reg = <0>;
2505 reg = <0 0xfead0000 0 0x10000>;
2516 #size-cells = <0>;
2518 port@0 {
2519 reg = <0>;
2536 reg = <0 0xfeb00000 0 0x80000>;
2542 clock-names = "du.0", "du.1", "du.3";
2544 reset-names = "du.0", "du.3";
2547 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2551 #size-cells = <0>;
2553 port@0 {
2554 reg = <0>;
2575 reg = <0 0xfeb90000 0 0x14>;
2583 #size-cells = <0>;
2585 port@0 {
2586 reg = <0>;
2601 reg = <0 0xfff00044 0 4>;
2609 thermal-sensors = <&tsc 0>;
2645 cooling-device = <&a57_0 0 2>;
2676 #clock-cells = <0>;
2677 clock-frequency = <0>;
2682 #clock-cells = <0>;
2683 clock-frequency = <0>;