Lines Matching +full:0 +full:x10020000
12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
50 reg = <0x00 0x01820000 0x00 0x10000>;
51 socionext,synquacer-pre-its = <0x1000000 0x400000>;
59 reg = <0x0 0x900000 0x0 0x2000>;
69 mux-controls = <&serdes_mux 0>;
74 reg = <0x0 0x910000 0x0 0x2000>;
89 reg = <0x00 0x02800000 0x00 0x100>;
100 reg = <0x00 0x02810000 0x00 0x100>;
110 reg = <0x00 0x02820000 0x00 0x100>;
120 reg = <0x0 0x4e00000 0x0 0x1200>;
124 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
127 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
128 <&main_udmap 0x4001>;
133 reg = <0x0 0x4e10000 0x0 0x7d>;
141 reg = <0x0 0x11c000 0x0 0x2e4>;
144 pinctrl-single,function-mask = <0xffffffff>;
149 reg = <0x0 0x11c2e8 0x0 0x24>;
152 pinctrl-single,function-mask = <0xffffffff>;
157 reg = <0x0 0x2000000 0x0 0x100>;
160 #size-cells = <0>;
168 reg = <0x0 0x2010000 0x0 0x100>;
171 #size-cells = <0>;
179 reg = <0x0 0x2020000 0x0 0x100>;
182 #size-cells = <0>;
190 reg = <0x0 0x2030000 0x0 0x100>;
193 #size-cells = <0>;
202 reg = <0x0 0x03100000 0x0 0x60>;
204 clocks = <&k3_clks 39 0>;
210 reg = <0x0 0x2100000 0x0 0x400>;
215 #size-cells = <0>;
216 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
222 reg = <0x0 0x2110000 0x0 0x400>;
227 #size-cells = <0>;
234 reg = <0x0 0x2120000 0x0 0x400>;
239 #size-cells = <0>;
244 reg = <0x0 0x2130000 0x0 0x400>;
249 #size-cells = <0>;
254 reg = <0x0 0x2140000 0x0 0x400>;
259 #size-cells = <0>;
264 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
266 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
271 ti,otap-del-sel-legacy = <0x0>;
272 ti,otap-del-sel-mmc-hs = <0x0>;
273 ti,otap-del-sel-sd-hs = <0x0>;
274 ti,otap-del-sel-sdr12 = <0x0>;
275 ti,otap-del-sel-sdr25 = <0x0>;
276 ti,otap-del-sel-sdr50 = <0x8>;
277 ti,otap-del-sel-sdr104 = <0x7>;
278 ti,otap-del-sel-ddr50 = <0x5>;
279 ti,otap-del-sel-ddr52 = <0x5>;
280 ti,otap-del-sel-hs200 = <0x5>;
281 ti,otap-del-sel-hs400 = <0x0>;
282 ti,trm-icp = <0x8>;
288 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
290 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
293 ti,otap-del-sel-legacy = <0x0>;
294 ti,otap-del-sel-mmc-hs = <0x0>;
295 ti,otap-del-sel-sd-hs = <0x0>;
296 ti,otap-del-sel-sdr12 = <0x0>;
297 ti,otap-del-sel-sdr25 = <0x0>;
298 ti,otap-del-sel-sdr50 = <0x8>;
299 ti,otap-del-sel-sdr104 = <0x7>;
300 ti,otap-del-sel-ddr50 = <0x4>;
301 ti,otap-del-sel-ddr52 = <0x4>;
302 ti,otap-del-sel-hs200 = <0x7>;
303 ti,clkbuf-sel = <0x7>;
304 ti,otap-del-sel = <0x2>;
305 ti,trm-icp = <0x8>;
312 reg = <0 0x00100000 0 0x1c000>;
315 ranges = <0x0 0x0 0x00100000 0x1c000>;
319 reg = <0x00004060 0x4>;
324 reg = <0x00004070 0x4>;
329 reg = <0x00000210 0x4>;
334 reg = <0x00004080 0x4>;
339 reg = <0x00004090 0x4>;
345 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
346 <0x4090 0x3>; /* SERDES1 lane select */
351 reg = <0x0000041e0 0x14>;
356 reg = <0x4140 0x18>;
363 reg = <0x0 0x4000000 0x0 0x4000>;
366 ranges = <0x0 0x0 0x4000000 0x20000>;
377 reg = <0x10000 0x10000>;
394 reg = <0x0 0x4100000 0x0 0x54>;
395 syscon-phy-power = <&scm_conf 0x4000>;
396 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
398 #phy-cells = <0>;
403 reg = <0x0 0x4020000 0x0 0x4000>;
406 ranges = <0x0 0x0 0x4020000 0x20000>;
416 reg = <0x10000 0x10000>;
432 reg = <0x0 0x4110000 0x0 0x54>;
433 syscon-phy-power = <&scm_conf 0x4020>;
434 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
436 #phy-cells = <0>;
447 ti,interrupt-ranges = <0 392 32>;
468 ti,interrupt-ranges = <0 64 64>,
474 reg = <0x0 0x33d00000 0x0 0x100000>;
480 ti,interrupt-ranges = <0 0 256>;
487 reg = <0x00 0x32c00000 0x00 0x100000>,
488 <0x00 0x32400000 0x00 0x100000>,
489 <0x00 0x32800000 0x00 0x100000>;
496 reg = <0x00 0x30e00000 0x00 0x1000>;
502 reg = <0x00 0x31f80000 0x00 0x200>;
511 reg = <0x00 0x31f81000 0x00 0x200>;
520 reg = <0x00 0x31f82000 0x00 0x200>;
529 reg = <0x00 0x31f83000 0x00 0x200>;
538 reg = <0x00 0x31f84000 0x00 0x200>;
547 reg = <0x00 0x31f85000 0x00 0x200>;
556 reg = <0x00 0x31f86000 0x00 0x200>;
565 reg = <0x00 0x31f87000 0x00 0x200>;
574 reg = <0x00 0x31f88000 0x00 0x200>;
583 reg = <0x00 0x31f89000 0x00 0x200>;
592 reg = <0x00 0x31f8a000 0x00 0x200>;
601 reg = <0x00 0x31f8b000 0x00 0x200>;
610 reg = <0x0 0x3c000000 0x0 0x400000>,
611 <0x0 0x38000000 0x0 0x400000>,
612 <0x0 0x31120000 0x0 0x100>,
613 <0x0 0x33000000 0x0 0x40000>;
616 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
625 reg = <0x0 0x31150000 0x0 0x100>,
626 <0x0 0x34000000 0x0 0x100000>,
627 <0x0 0x35000000 0x0 0x100000>;
636 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
637 <0xd>; /* TX_CHAN */
638 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
639 <0xa>; /* RX_CHAN */
640 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
645 reg = <0x0 0x310d0000 0x0 0x400>;
655 #clock-cells = <0>;
668 reg = <0x0 0x600000 0x0 0x100>;
676 ti,davinci-gpio-unbanked = <0>;
677 clocks = <&k3_clks 57 0>;
683 reg = <0x0 0x601000 0x0 0x100>;
691 ti,davinci-gpio-unbanked = <0>;
692 clocks = <&k3_clks 58 0>;
698 …reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0…
703 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
704 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
707 bus-range = <0x0 0xff>;
712 msi-map = <0x0 &gic_its 0x0 0x10000>;
717 …reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x…
730 …reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0…
735 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
736 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
739 bus-range = <0x0 0xff>;
744 msi-map = <0x0 &gic_its 0x10000 0x10000>;
749 …reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x…
762 reg = <0x0 0x02b00000 0x0 0x2000>,
763 <0x0 0x02b08000 0x0 0x1000>;
769 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
772 clocks = <&k3_clks 104 0>;
781 reg = <0x0 0x02b10000 0x0 0x2000>,
782 <0x0 0x02b18000 0x0 0x1000>;
788 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
791 clocks = <&k3_clks 105 0>;
800 reg = <0x0 0x02b20000 0x0 0x2000>,
801 <0x0 0x02b28000 0x0 0x1000>;
807 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
810 clocks = <&k3_clks 106 0>;
819 reg = <0x0 0x06f03000 0x0 0x400>,
820 <0x0 0x06f03800 0x0 0x40>;
824 ti,camerrx-control = <&scm_conf 0x40c0>;
826 clocks = <&k3_clks 2 0>;
831 #size-cells = <0>;
833 csi2_0: port@0 {
834 reg = <0>;
841 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
842 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
843 <0x0 0x04a06000 0x0 0x1000>, /* vid */
844 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
845 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
846 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
847 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
876 #size-cells = <0>;
883 reg = <0x0 0x3000000 0x0 0x100>;
885 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
892 reg = <0x0 0x3010000 0x0 0x100>;
894 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
901 reg = <0x0 0x3020000 0x0 0x100>;
903 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
910 reg = <0x0 0x3030000 0x0 0x100>;
912 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
919 reg = <0x0 0x3040000 0x0 0x100>;
921 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
928 reg = <0x0 0x3050000 0x0 0x100>;
930 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;