Lines Matching +full:0 +full:x81800000
13 #clock-cells = <0>;
15 clock-frequency = <0>;
19 #clock-cells = <0>;
21 clock-frequency = <0>;
28 reg = <0x0 0x70000000 0x0 0x800000>;
31 ranges = <0x0 0x0 0x70000000 0x800000>;
33 atf-sram@0 {
34 reg = <0x0 0x20000>;
40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
43 ranges = <0x0 0x0 0x00100000 0x1c000>;
47 reg = <0x00004070 0x4>;
50 ranges = <0x4070 0x4070 0x4>;
55 reg = <0x00004074 0x4>;
58 ranges = <0x4074 0x4074 0x4>;
63 reg = <0x00004078 0x4>;
66 ranges = <0x4078 0x4078 0x4>;
71 reg = <0x0000407c 0x4>;
74 ranges = <0x407c 0x407c 0x4>;
79 reg = <0x00004080 0x50>;
81 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
82 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
83 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
84 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
85 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
98 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
99 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
110 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
111 <0x00 0x01900000 0x00 0x100000>, /* GICR */
112 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
113 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
114 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
121 reg = <0x00 0x01820000 0x00 0x10000>;
122 socionext,synquacer-pre-its = <0x1000000 0x400000>;
157 ti,interrupt-ranges = <0 64 64>,
164 reg = <0x0 0x33d00000 0x0 0x100000>;
170 ti,interrupt-ranges = <0 0 256>;
177 reg = <0x00 0x32c00000 0x00 0x100000>,
178 <0x00 0x32400000 0x00 0x100000>,
179 <0x00 0x32800000 0x00 0x100000>;
186 reg = <0x0 0x36600000 0x0 0x100000>;
196 reg = <0x00 0x30e00000 0x00 0x1000>;
202 reg = <0x00 0x31f80000 0x00 0x200>;
211 reg = <0x00 0x31f81000 0x00 0x200>;
220 reg = <0x00 0x31f82000 0x00 0x200>;
229 reg = <0x00 0x31f83000 0x00 0x200>;
238 reg = <0x00 0x31f84000 0x00 0x200>;
247 reg = <0x00 0x31f85000 0x00 0x200>;
256 reg = <0x00 0x31f86000 0x00 0x200>;
265 reg = <0x00 0x31f87000 0x00 0x200>;
274 reg = <0x00 0x31f88000 0x00 0x200>;
283 reg = <0x00 0x31f89000 0x00 0x200>;
292 reg = <0x00 0x31f8a000 0x00 0x200>;
301 reg = <0x00 0x31f8b000 0x00 0x200>;
310 reg = <0x0 0x3c000000 0x0 0x400000>,
311 <0x0 0x38000000 0x0 0x400000>,
312 <0x0 0x31120000 0x0 0x100>,
313 <0x0 0x33000000 0x0 0x40000>;
316 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
324 reg = <0x0 0x31150000 0x0 0x100>,
325 <0x0 0x34000000 0x0 0x100000>,
326 <0x0 0x35000000 0x0 0x100000>;
335 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
336 <0x0f>, /* TX_HCHAN */
337 <0x10>; /* TX_UHCHAN */
338 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
339 <0x0b>, /* RX_HCHAN */
340 <0x0c>; /* RX_UHCHAN */
341 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
346 reg = <0x0 0x310d0000 0x0 0x400>;
359 reg = <0x0 0x4e00000 0x0 0x1200>;
363 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
367 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
368 <&main_udmap 0x4001>;
373 reg = <0x0 0x4e10000 0x0 0x7d>;
381 /* Proxy 0 addressing */
382 reg = <0x0 0x11c000 0x0 0x2b4>;
385 pinctrl-single,function-mask = <0xffffffff>;
395 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
399 ranges = <0x5000000 0x0 0x5000000 0x10000>;
403 #clock-cells = <0>;
409 clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
410 #clock-cells = <0>;
412 assigned-clock-parents = <&k3_clks 292 0>;
416 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
417 #clock-cells = <0>;
424 #clock-cells = <0>;
429 #clock-cells = <0>;
435 reg = <0x5000000 0x10000>;
437 #size-cells = <0>;
438 resets = <&serdes_wiz0 0>;
452 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
456 ranges = <0x5010000 0x0 0x5010000 0x10000>;
460 #clock-cells = <0>;
466 clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
467 #clock-cells = <0>;
469 assigned-clock-parents = <&k3_clks 293 0>;
473 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
474 #clock-cells = <0>;
481 #clock-cells = <0>;
486 #clock-cells = <0>;
492 reg = <0x5010000 0x10000>;
494 #size-cells = <0>;
495 resets = <&serdes_wiz1 0>;
509 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
513 ranges = <0x5020000 0x0 0x5020000 0x10000>;
517 #clock-cells = <0>;
523 clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
524 #clock-cells = <0>;
526 assigned-clock-parents = <&k3_clks 294 0>;
530 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
531 #clock-cells = <0>;
538 #clock-cells = <0>;
543 #clock-cells = <0>;
549 reg = <0x5020000 0x10000>;
551 #size-cells = <0>;
552 resets = <&serdes_wiz2 0>;
566 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
570 ranges = <0x5030000 0x0 0x5030000 0x10000>;
574 #clock-cells = <0>;
580 clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
581 #clock-cells = <0>;
583 assigned-clock-parents = <&k3_clks 295 0>;
587 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
588 #clock-cells = <0>;
595 #clock-cells = <0>;
600 #clock-cells = <0>;
606 reg = <0x5030000 0x10000>;
608 #size-cells = <0>;
609 resets = <&serdes_wiz3 0>;
618 reg = <0x00 0x02900000 0x00 0x1000>,
619 <0x00 0x02907000 0x00 0x400>,
620 <0x00 0x0d000000 0x00 0x00800000>,
621 <0x00 0x10000000 0x00 0x00001000>;
634 bus-range = <0x0 0xff>;
635 vendor-id = <0x104c>;
636 device-id = <0xb00d>;
637 msi-map = <0x0 &gic_its 0x0 0x10000>;
639 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
640 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
641 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
646 reg = <0x00 0x02900000 0x00 0x1000>,
647 <0x00 0x02907000 0x00 0x400>,
648 <0x00 0x0d000000 0x00 0x00800000>,
649 <0x00 0x10000000 0x00 0x08000000>;
661 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
667 reg = <0x00 0x02910000 0x00 0x1000>,
668 <0x00 0x02917000 0x00 0x400>,
669 <0x00 0x0d800000 0x00 0x00800000>,
670 <0x00 0x18000000 0x00 0x00001000>;
683 bus-range = <0x0 0xff>;
684 vendor-id = <0x104c>;
685 device-id = <0xb00d>;
686 msi-map = <0x0 &gic_its 0x10000 0x10000>;
688 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
689 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
690 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
695 reg = <0x00 0x02910000 0x00 0x1000>,
696 <0x00 0x02917000 0x00 0x400>,
697 <0x00 0x0d800000 0x00 0x00800000>,
698 <0x00 0x18000000 0x00 0x08000000>;
710 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
716 reg = <0x00 0x02920000 0x00 0x1000>,
717 <0x00 0x02927000 0x00 0x400>,
718 <0x00 0x0e000000 0x00 0x00800000>,
719 <0x44 0x00000000 0x00 0x00001000>;
732 bus-range = <0x0 0xff>;
733 vendor-id = <0x104c>;
734 device-id = <0xb00d>;
735 msi-map = <0x0 &gic_its 0x20000 0x10000>;
737 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
738 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
739 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
744 reg = <0x00 0x02920000 0x00 0x1000>,
745 <0x00 0x02927000 0x00 0x400>,
746 <0x00 0x0e000000 0x00 0x00800000>,
747 <0x44 0x00000000 0x00 0x08000000>;
759 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
765 reg = <0x00 0x02930000 0x00 0x1000>,
766 <0x00 0x02937000 0x00 0x400>,
767 <0x00 0x0e800000 0x00 0x00800000>,
768 <0x44 0x10000000 0x00 0x00001000>;
781 bus-range = <0x0 0xff>;
782 vendor-id = <0x104c>;
783 device-id = <0xb00d>;
784 msi-map = <0x0 &gic_its 0x30000 0x10000>;
786 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
787 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
788 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
793 reg = <0x00 0x02930000 0x00 0x1000>,
794 <0x00 0x02937000 0x00 0x400>,
795 <0x00 0x0e800000 0x00 0x00800000>,
796 <0x44 0x10000000 0x00 0x08000000>;
808 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
816 reg = <0x00 0x02800000 0x00 0x100>;
823 clocks = <&k3_clks 146 0>;
829 reg = <0x00 0x02810000 0x00 0x100>;
836 clocks = <&k3_clks 278 0>;
842 reg = <0x00 0x02820000 0x00 0x100>;
849 clocks = <&k3_clks 279 0>;
855 reg = <0x00 0x02830000 0x00 0x100>;
862 clocks = <&k3_clks 280 0>;
868 reg = <0x00 0x02840000 0x00 0x100>;
875 clocks = <&k3_clks 281 0>;
881 reg = <0x00 0x02850000 0x00 0x100>;
888 clocks = <&k3_clks 282 0>;
894 reg = <0x00 0x02860000 0x00 0x100>;
901 clocks = <&k3_clks 283 0>;
907 reg = <0x00 0x02870000 0x00 0x100>;
914 clocks = <&k3_clks 284 0>;
920 reg = <0x00 0x02880000 0x00 0x100>;
927 clocks = <&k3_clks 285 0>;
933 reg = <0x00 0x02890000 0x00 0x100>;
940 clocks = <&k3_clks 286 0>;
946 reg = <0x0 0x00600000 0x0 0x100>;
955 ti,davinci-gpio-unbanked = <0>;
957 clocks = <&k3_clks 105 0>;
963 reg = <0x0 0x00601000 0x0 0x100>;
971 ti,davinci-gpio-unbanked = <0>;
973 clocks = <&k3_clks 106 0>;
979 reg = <0x0 0x00610000 0x0 0x100>;
988 ti,davinci-gpio-unbanked = <0>;
990 clocks = <&k3_clks 107 0>;
996 reg = <0x0 0x00611000 0x0 0x100>;
1004 ti,davinci-gpio-unbanked = <0>;
1006 clocks = <&k3_clks 108 0>;
1012 reg = <0x0 0x00620000 0x0 0x100>;
1021 ti,davinci-gpio-unbanked = <0>;
1023 clocks = <&k3_clks 109 0>;
1029 reg = <0x0 0x00621000 0x0 0x100>;
1037 ti,davinci-gpio-unbanked = <0>;
1039 clocks = <&k3_clks 110 0>;
1045 reg = <0x0 0x00630000 0x0 0x100>;
1054 ti,davinci-gpio-unbanked = <0>;
1056 clocks = <&k3_clks 111 0>;
1062 reg = <0x0 0x00631000 0x0 0x100>;
1070 ti,davinci-gpio-unbanked = <0>;
1072 clocks = <&k3_clks 112 0>;
1078 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1082 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
1088 ti,otap-del-sel = <0x2>;
1089 ti,trm-icp = <0x8>;
1090 ti,strobe-sel = <0x77>;
1096 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1100 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
1101 assigned-clocks = <&k3_clks 92 0>;
1103 ti,otap-del-sel = <0x2>;
1104 ti,trm-icp = <0x8>;
1105 ti,clkbuf-sel = <0x7>;
1112 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1116 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
1117 assigned-clocks = <&k3_clks 93 0>;
1119 ti,otap-del-sel = <0x2>;
1120 ti,trm-icp = <0x8>;
1121 ti,clkbuf-sel = <0x7>;
1128 reg = <0x00 0x4104000 0x00 0x100>;
1141 reg = <0x00 0x6000000 0x00 0x10000>,
1142 <0x00 0x6010000 0x00 0x10000>,
1143 <0x00 0x6020000 0x00 0x10000>;
1145 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1147 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1158 reg = <0x00 0x4114000 0x00 0x100>;
1171 reg = <0x00 0x6400000 0x00 0x10000>,
1172 <0x00 0x6410000 0x00 0x10000>,
1173 <0x00 0x6420000 0x00 0x10000>;
1175 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1177 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1188 reg = <0x0 0x2000000 0x0 0x100>;
1191 #size-cells = <0>;
1193 clocks = <&k3_clks 187 0>;
1199 reg = <0x0 0x2010000 0x0 0x100>;
1202 #size-cells = <0>;
1204 clocks = <&k3_clks 188 0>;
1210 reg = <0x0 0x2020000 0x0 0x100>;
1213 #size-cells = <0>;
1215 clocks = <&k3_clks 189 0>;
1221 reg = <0x0 0x2030000 0x0 0x100>;
1224 #size-cells = <0>;
1226 clocks = <&k3_clks 190 0>;
1232 reg = <0x0 0x2040000 0x0 0x100>;
1235 #size-cells = <0>;
1237 clocks = <&k3_clks 191 0>;
1243 reg = <0x0 0x2050000 0x0 0x100>;
1246 #size-cells = <0>;
1248 clocks = <&k3_clks 192 0>;
1254 reg = <0x0 0x2060000 0x0 0x100>;
1257 #size-cells = <0>;
1259 clocks = <&k3_clks 193 0>;
1265 reg = <0x0 0x4e80000 0x0 0x100>;
1276 reg = <0x0 0x4e84000 0x0 0x10000>;
1279 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1288 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1289 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1290 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1291 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1293 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1294 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1295 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1296 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1298 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1299 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1300 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1301 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1303 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1304 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1305 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1306 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1307 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1316 clocks = <&k3_clks 152 0>,
1338 #size-cells = <0>;
1344 reg = <0x0 0x02b00000 0x0 0x2000>,
1345 <0x0 0x02b08000 0x0 0x1000>;
1351 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1363 reg = <0x0 0x02b10000 0x0 0x2000>,
1364 <0x0 0x02b18000 0x0 0x1000>;
1370 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1382 reg = <0x0 0x02b20000 0x0 0x2000>,
1383 <0x0 0x02b28000 0x0 0x1000>;
1389 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1401 reg = <0x0 0x02b30000 0x0 0x2000>,
1402 <0x0 0x02b38000 0x0 0x1000>;
1408 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1420 reg = <0x0 0x02b40000 0x0 0x2000>,
1421 <0x0 0x02b48000 0x0 0x1000>;
1427 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1439 reg = <0x0 0x02b50000 0x0 0x2000>,
1440 <0x0 0x02b58000 0x0 0x1000>;
1446 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1458 reg = <0x0 0x02b60000 0x0 0x2000>,
1459 <0x0 0x02b68000 0x0 0x1000>;
1465 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1477 reg = <0x0 0x02b70000 0x0 0x2000>,
1478 <0x0 0x02b78000 0x0 0x1000>;
1484 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1496 reg = <0x0 0x02b80000 0x0 0x2000>,
1497 <0x0 0x02b88000 0x0 0x1000>;
1503 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1515 reg = <0x0 0x02b90000 0x0 0x2000>,
1516 <0x0 0x02b98000 0x0 0x1000>;
1522 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1534 reg = <0x0 0x02ba0000 0x0 0x2000>,
1535 <0x0 0x02ba8000 0x0 0x1000>;
1541 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1553 reg = <0x0 0x02bb0000 0x0 0x2000>,
1554 <0x0 0x02bb8000 0x0 0x1000>;
1560 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
1572 reg = <0x0 0x2200000 0x0 0x100>;
1581 reg = <0x0 0x2210000 0x0 0x100>;
1590 reg = <0x4d 0x80800000 0x00 0x00048000>,
1591 <0x4d 0x80e00000 0x00 0x00008000>,
1592 <0x4d 0x80f00000 0x00 0x00008000>;
1596 ti,sci-proc-ids = <0x03 0xff>;
1603 reg = <0x4d 0x81800000 0x00 0x00048000>,
1604 <0x4d 0x81e00000 0x00 0x00008000>,
1605 <0x4d 0x81f00000 0x00 0x00008000>;
1609 ti,sci-proc-ids = <0x04 0xff>;
1616 reg = <0x00 0x64800000 0x00 0x00080000>,
1617 <0x00 0x64e00000 0x00 0x0000c000>;
1621 ti,sci-proc-ids = <0x30 0xff>;