Lines Matching +full:0 +full:x01800000
29 #define VEC_RESETSP (0)
100 #define PS_T (0x8000)
101 #define PS_S (0x2000)
102 #define PS_M (0x1000)
103 #define PS_C (0x0001)
107 #define FC (0x8000)
108 #define FB (0x4000)
109 #define RC (0x2000)
110 #define RB (0x1000)
111 #define DF (0x0100)
112 #define RM (0x0080)
113 #define RW (0x0040)
114 #define SZ (0x0030)
115 #define DFC (0x0007)
119 #define MMU_B (0x8000) /* bus error */
120 #define MMU_L (0x4000) /* limit violation */
121 #define MMU_S (0x2000) /* supervisor violation */
122 #define MMU_WP (0x0800) /* write-protected */
123 #define MMU_I (0x0400) /* invalid descriptor */
124 #define MMU_M (0x0200) /* ATC entry modified */
125 #define MMU_T (0x0040) /* transparent translation */
126 #define MMU_NUM (0x0007) /* number of levels traversed */
130 #define CP_040 (0x8000)
131 #define CU_040 (0x4000)
132 #define CT_040 (0x2000)
133 #define CM_040 (0x1000)
134 #define MA_040 (0x0800)
135 #define ATC_040 (0x0400)
136 #define LK_040 (0x0200)
137 #define RW_040 (0x0100)
138 #define SIZ_040 (0x0060)
139 #define TT_040 (0x0018)
140 #define TM_040 (0x0007)
143 #define WBV_040 (0x80)
144 #define WBSIZ_040 (0x60)
145 #define WBBYT_040 (0x20)
146 #define WBWRD_040 (0x40)
147 #define WBLNG_040 (0x00)
148 #define WBTT_040 (0x18)
149 #define WBTM_040 (0x07)
152 #define BA_SIZE_BYTE (0x20)
153 #define BA_SIZE_WORD (0x40)
154 #define BA_SIZE_LONG (0x00)
155 #define BA_SIZE_LINE (0x60)
158 #define BA_TT_MOVE16 (0x08)
161 #define MMU_B_040 (0x0800)
162 #define MMU_G_040 (0x0400)
163 #define MMU_S_040 (0x0080)
164 #define MMU_CM_040 (0x0060)
165 #define MMU_M_040 (0x0010)
166 #define MMU_WP_040 (0x0004)
167 #define MMU_T_040 (0x0002)
168 #define MMU_R_040 (0x0001)
171 #define MMU060_MA (0x08000000) /* misaligned */
172 #define MMU060_LK (0x02000000) /* locked transfer */
173 #define MMU060_RW (0x01800000) /* read/write */
174 # define MMU060_RW_W (0x00800000) /* write */
175 # define MMU060_RW_R (0x01000000) /* read */
176 # define MMU060_RW_RMW (0x01800000) /* read/modify/write */
177 # define MMU060_W (0x00800000) /* general write, includes rmw */
178 #define MMU060_SIZ (0x00600000) /* transfer size */
179 #define MMU060_TT (0x00180000) /* transfer type (TT) bits */
180 #define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */
181 #define MMU060_IO (0x00008000) /* instruction or operand */
182 #define MMU060_PBE (0x00004000) /* push buffer bus error */
183 #define MMU060_SBE (0x00002000) /* store buffer bus error */
184 #define MMU060_PTA (0x00001000) /* pointer A fault */
185 #define MMU060_PTB (0x00000800) /* pointer B fault */
186 #define MMU060_IL (0x00000400) /* double indirect descr fault */
187 #define MMU060_PF (0x00000200) /* page fault (invalid descr) */
188 #define MMU060_SP (0x00000100) /* supervisor protection */
189 #define MMU060_WP (0x00000080) /* write protection */
190 #define MMU060_TWE (0x00000040) /* bus error on table search */
191 #define MMU060_RE (0x00000020) /* bus error on read */
192 #define MMU060_WE (0x00000010) /* bus error on write */
193 #define MMU060_TTR (0x00000008) /* error caused by TTR translation */
194 #define MMU060_BPE (0x00000004) /* branch prediction error */
195 #define MMU060_SEE (0x00000001) /* software emulated error */
231 unsigned long wb1dpd0; /* write back 1 data/push data 0*/