Lines Matching refs:pvr
16 unsigned pvr[12]; member
122 #define PVR_IS_FULL(_pvr) (_pvr.pvr[0] & PVR0_PVR_FULL_MASK)
123 #define PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & PVR0_USE_BARREL_MASK)
124 #define PVR_USE_DIV(_pvr) (_pvr.pvr[0] & PVR0_USE_DIV_MASK)
125 #define PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
126 #define PVR_USE_FPU(_pvr) (_pvr.pvr[0] & PVR0_USE_FPU_MASK)
127 #define PVR_USE_FPU2(_pvr) (_pvr.pvr[2] & PVR2_USE_FPU2_MASK)
128 #define PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
129 #define PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
130 #define PVR_VERSION(_pvr) ((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
131 #define PVR_USER1(_pvr) (_pvr.pvr[0] & PVR0_USER1_MASK)
132 #define PVR_USER2(_pvr) (_pvr.pvr[1] & PVR1_USER2_MASK)
134 #define PVR_D_OPB(_pvr) (_pvr.pvr[2] & PVR2_D_OPB_MASK)
135 #define PVR_D_LMB(_pvr) (_pvr.pvr[2] & PVR2_D_LMB_MASK)
136 #define PVR_I_OPB(_pvr) (_pvr.pvr[2] & PVR2_I_OPB_MASK)
137 #define PVR_I_LMB(_pvr) (_pvr.pvr[2] & PVR2_I_LMB_MASK)
139 (_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
141 (_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
142 #define PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_MSR_INSTR)
143 #define PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_PCMP_INSTR)
144 #define PVR_AREA_OPTIMISED(_pvr) (_pvr.pvr[2] & PVR2_AREA_OPTIMISED)
145 #define PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & PVR2_USE_MUL64_MASK)
147 (_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
149 (_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
151 (_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
153 (_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
155 (_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
157 (_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
158 #define PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_FPU_EXC_MASK)
159 #define PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_USE_EXTEND_FSL)
161 #define PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)
163 ((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
165 ((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
167 ((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
168 #define PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)
171 ((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
173 (_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
175 (_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
177 (1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
179 (1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
182 ((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
183 #define PVR_DCACHE_USE_FSL(_pvr) (_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
185 (_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
188 (1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
190 (1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
193 ((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
196 (_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
198 (_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
200 (_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
202 (_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
205 ((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
208 (_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
211 #define PVR_USE_MMU(_pvr) ((_pvr.pvr[11] & PVR11_USE_MMU) >> 30)
212 #define PVR_MMU_ITLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)
213 #define PVR_MMU_DTLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
214 #define PVR_MMU_TLB_ACCESS(_pvr) (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
215 #define PVR_MMU_ZONES(_pvr) (_pvr.pvr[11] & PVR11_MMU_ZONES)
216 #define PVR_MMU_PRIVINS(pvr) (pvr.pvr[11] & PVR11_MMU_PRIVINS) argument
219 #define PVR_ENDIAN(_pvr) (_pvr.pvr[0] & PVR0_ENDI)
222 void get_pvr(struct pvr_s *pvr);