Lines Matching +full:0 +full:x100
13 #define RT3883_SDRAM_BASE 0x00000000
14 #define RT3883_SYSC_BASE 0x10000000
15 #define RT3883_TIMER_BASE 0x10000100
16 #define RT3883_INTC_BASE 0x10000200
17 #define RT3883_MEMC_BASE 0x10000300
18 #define RT3883_UART0_BASE 0x10000500
19 #define RT3883_PIO_BASE 0x10000600
20 #define RT3883_FSCC_BASE 0x10000700
21 #define RT3883_NANDC_BASE 0x10000810
22 #define RT3883_I2C_BASE 0x10000900
23 #define RT3883_I2S_BASE 0x10000a00
24 #define RT3883_SPI_BASE 0x10000b00
25 #define RT3883_UART1_BASE 0x10000c00
26 #define RT3883_PCM_BASE 0x10002000
27 #define RT3883_GDMA_BASE 0x10002800
28 #define RT3883_CODEC1_BASE 0x10003000
29 #define RT3883_CODEC2_BASE 0x10003800
30 #define RT3883_FE_BASE 0x10100000
31 #define RT3883_ROM_BASE 0x10118000
32 #define RT3883_USBDEV_BASE 0x10112000
33 #define RT3883_PCI_BASE 0x10140000
34 #define RT3883_WLAN_BASE 0x10180000
35 #define RT3883_USBHOST_BASE 0x101c0000
36 #define RT3883_BOOT_BASE 0x1c000000
37 #define RT3883_SRAM_BASE 0x1e000000
38 #define RT3883_PCIMEM_BASE 0x20000000
41 #define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
43 #define RT3883_SYSC_SIZE 0x100
44 #define RT3883_TIMER_SIZE 0x100
45 #define RT3883_INTC_SIZE 0x100
46 #define RT3883_MEMC_SIZE 0x100
47 #define RT3883_UART0_SIZE 0x100
48 #define RT3883_UART1_SIZE 0x100
49 #define RT3883_PIO_SIZE 0x100
50 #define RT3883_FSCC_SIZE 0x100
51 #define RT3883_NANDC_SIZE 0x0f0
52 #define RT3883_I2C_SIZE 0x100
53 #define RT3883_I2S_SIZE 0x100
54 #define RT3883_SPI_SIZE 0x100
55 #define RT3883_PCM_SIZE 0x800
56 #define RT3883_GDMA_SIZE 0x800
57 #define RT3883_CODEC1_SIZE 0x800
58 #define RT3883_CODEC2_SIZE 0x800
59 #define RT3883_FE_SIZE 0x10000
60 #define RT3883_ROM_SIZE 0x4000
61 #define RT3883_USBDEV_SIZE 0x4000
62 #define RT3883_PCI_SIZE 0x40000
63 #define RT3883_WLAN_SIZE 0x40000
64 #define RT3883_USBHOST_SIZE 0x40000
69 #define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
70 #define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
71 #define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
72 #define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
73 #define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
74 #define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
75 #define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
76 #define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
77 #define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
78 #define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
79 #define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
80 #define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
81 #define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
82 #define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
83 #define RT3883_SYSC_REG_PMU 0x88
84 #define RT3883_SYSC_REG_PMU1 0x8c
86 #define RT3883_CHIP_NAME0 0x38335452
87 #define RT3883_CHIP_NAME1 0x20203338
89 #define RT3883_REVID_VER_ID_MASK 0x0f
91 #define RT3883_REVID_ECO_ID_MASK 0x0f
95 #define RT3883_SYSCFG0_CPUCLK_MASK 0x3
96 #define RT3883_SYSCFG0_CPUCLK_250 0x0
97 #define RT3883_SYSCFG0_CPUCLK_384 0x1
98 #define RT3883_SYSCFG0_CPUCLK_480 0x2
99 #define RT3883_SYSCFG0_CPUCLK_500 0x3
113 #define RT3883_GPIO_MODE_UART0_MASK 0x7
115 #define RT3883_GPIO_MODE_UARTF 0x0
116 #define RT3883_GPIO_MODE_PCM_UARTF 0x1
117 #define RT3883_GPIO_MODE_PCM_I2S 0x2
118 #define RT3883_GPIO_MODE_I2S_UARTF 0x3
119 #define RT3883_GPIO_MODE_PCM_GPIO 0x4
120 #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
121 #define RT3883_GPIO_MODE_GPIO_I2S 0x6
122 #define RT3883_GPIO_MODE_GPIO 0x7
124 #define RT3883_GPIO_MODE_I2C 0
133 #define RT3883_GPIO_MODE_PCI_MASK 0x7
136 #define RT3883_GPIO_MODE_LNA_A_MASK 0x3
138 #define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
141 #define RT3883_GPIO_MODE_LNA_G_MASK 0x3
143 #define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
218 #define RT3883_RSTCTRL_SYS BIT(0)
220 #define RT3883_INTC_INT_SYSCTL BIT(0)
236 #define RT3883_FSCC_REG_FLASH_CFG0 0x00
237 #define RT3883_FSCC_REG_FLASH_CFG1 0x04
238 #define RT3883_FSCC_REG_CODEC_CFG0 0x40
239 #define RT3883_FSCC_REG_CODEC_CFG1 0x44
242 #define RT3883_FLASH_CFG_WIDTH_MASK 0x3
243 #define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
244 #define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
245 #define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
247 #define RT3883_SDRAM_BASE 0x00000000