Lines Matching +full:0 +full:x02000
22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
26 #define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
28 #define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30 #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
31 #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
40 u32 _unused0[0x1000/4 - 2]; /* padding */
45 #define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */
46 #define HPC3_PDMACTRL_ISACT 0x00000002 /* channel active */
48 #define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */
49 #define HPC3_PDMACTRL_RCV 0x00000004 /* direction is receive */
50 #define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */
51 #define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */
52 #define HPC3_PDMACTRL_LD 0x00000020 /* load enable for ACT */
53 #define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
55 #define HPC3_PDMACTRL_FB 0x003f0000 /* Ptr to beginning of fifo */
56 #define HPC3_PDMACTRL_FE 0x3f000000 /* Ptr to end of fifo */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
67 #define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
68 #define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */
69 #define HPC3_SBCD_EOX 0x00008000 /* Indicates this is last buf in chain */
72 #define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */
73 #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
74 #define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
75 #define HPC3_SCTRL_FLUSH 0x08 /* Tells HPC3 to flush scsi fifos */
76 #define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
77 #define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */
78 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
79 #define HPC3_SCTRL_PERR 0x80 /* Bad parity on HPC3 iface to scsi controller */
84 #define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
85 #define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */
86 #define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */
87 #define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */
88 #define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
90 #define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
91 #define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
92 #define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
93 #define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
96 #define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */
97 #define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */
98 #define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */
99 #define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */
100 #define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
101 #define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
102 #define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
103 #define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
105 u32 _unused1[0x1000/4 - 6]; /* padding */
113 u32 _unused0[0x1000/4 - 2]; /* padding */
115 #define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
116 #define HPC3_ERXBCD_XIE 0x20000000 /* HPC3 interrupts cpu at end of this buf */
117 #define HPC3_ERXBCD_EOX 0x80000000 /* flags this as end of descriptor chain */
120 #define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
121 #define HPC3_ERXCTRL_STAT6 0x00000040 /* Rdonly irq status */
122 #define HPC3_ERXCTRL_STAT7 0x00000080 /* Rdonlt old/new status bit from Seeq */
123 #define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
124 #define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
125 #define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
126 #define HPC3_ERXCTRL_RBO 0x00000800 /* Receive buffer overflow if set to 1 */
132 #define HPC3_ERST_CRESET 0x1 /* Reset dma channel and external controller */
133 #define HPC3_ERST_CLRIRQ 0x2 /* Clear channel interrupt */
134 #define HPC3_ERST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */
137 #define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
138 #define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
139 #define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
140 #define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
141 #define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
142 #define HPC3_EDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */
143 #define HPC3_EDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */
144 #define HPC3_EDCFG_PTO 0x30000 /* Programmed timeout value for above two */
147 #define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
148 #define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
149 #define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
150 #define HPC3_EPCFG_TST 0x1000 /* Diagnostic ram test feature bit */
152 u32 _unused2[0x1000/4 - 8]; /* padding */
157 u32 _unused3[0x1000/4 - 2]; /* padding */
159 #define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */
160 #define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */
161 #define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */
162 #define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */
163 #define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */
166 #define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */
167 #define HPC3_ETXCTRL_STAT4 0x00000010 /* Indicate late collision occurred */
168 #define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */
169 #define HPC3_ETXCTRL_ENDIAN 0x00000100 /* DMA channel endian mode, 1=little 0=big */
170 #define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */
171 #define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */
175 u32 _unused4[0x1000/4 - 4]; /* padding */
191 u32 _unused0[0x18000/4];
196 * bits 4:0 of the status, and the second reg can only
200 volatile u32 istat0; /* Irq status, only bits <4:0> reliable. */
201 #define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */
202 #define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */
203 #define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */
206 #define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
207 #define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
210 #define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
211 #define HPC3_EEPROM_CSEL 0x02 /* Chip select */
212 #define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */
213 #define HPC3_EEPROM_DATO 0x08 /* Data out */
214 #define HPC3_EEPROM_DATI 0x10 /* Data in */
218 #define HPC3_BESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */
219 #define HPC3_BESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */
221 #define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */
223 u32 _unused1[0x14000/4 - 5]; /* padding */
226 volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */
227 u32 _unused2[0x7c00/4];
229 u32 _unused3[0x7c00/4];
231 u32 _unused4[0x3b00/4];
237 #define HPC3_DMACFG_D3R_MASK 0x00000001
238 #define HPC3_DMACFG_D3R_SHIFT 0
240 #define HPC3_DMACFG_D4R_MASK 0x0000001e
243 #define HPC3_DMACFG_D5R_MASK 0x000001e0
246 #define HPC3_DMACFG_D3W_MASK 0x00000200
249 #define HPC3_DMACFG_D4W_MASK 0x00003c00
252 #define HPC3_DMACFG_D5W_MASK 0x0003c000
255 #define HPC3_DMACFG_DS16 0x00040000
257 #define HPC3_DMACFG_EVENHI 0x00080000
259 #define HPC3_DMACFG_RTIME 0x00200000
261 #define HPC3_DMACFG_BURST_MASK 0x07c00000
264 #define HPC3_DMACFG_DRQLIVE 0x08000000
267 #define HPC3_PIOCFG_P2R_MASK 0x00001
268 #define HPC3_PIOCFG_P2R_SHIFT 0
270 #define HPC3_PIOCFG_P3R_MASK 0x0001e
273 #define HPC3_PIOCFG_P4R_MASK 0x001e0
276 #define HPC3_PIOCFG_P2W_MASK 0x00200
279 #define HPC3_PIOCFG_P3W_MASK 0x03c00
282 #define HPC3_PIOCFG_P4W_MASK 0x3c000
285 #define HPC3_PIOCFG_DS16 0x40000
287 #define HPC3_PIOCFG_EVENHI 0x80000
291 #define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */
293 u32 _unused5[0x0800/4 - 1];
295 #define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */
297 u32 _unused6[0x0800/4 - 1];
299 #define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */
301 u32 _unused7[0x1000/4 - 1];
312 #define HPC3_CHIP0_BASE 0x1fb80000 /* physical */
313 #define HPC3_CHIP1_BASE 0x1fb00000 /* physical */