Lines Matching +full:a +full:- +full:ilm
1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (C) 2005-2017 Andes Technology Corporation
20 #define ICM_CFG_offISET 0 /* I-cache sets (# of cache lines) per way */
21 #define ICM_CFG_offIWAY 3 /* I-cache ways */
22 #define ICM_CFG_offISZ 6 /* I-cache line size */
23 #define ICM_CFG_offILCK 9 /* I-cache locking support */
24 #define ICM_CFG_offILMB 10 /* On-chip ILM banks */
25 #define ICM_CFG_offBSAV 13 /* ILM base register alignment version */
38 #define DCM_CFG_offDSET 0 /* D-cache sets (# of cache lines) per way */
39 #define DCM_CFG_offDWAY 3 /* D-cache ways */
40 #define DCM_CFG_offDSZ 6 /* D-cache line size */
41 #define DCM_CFG_offDLCK 9 /* D-cache locking support */
42 #define DCM_CFG_offDLMB 10 /* On-chip DLM banks */
58 #define MMU_CFG_offFATB 7 /* Fully-associative or non-fully-associative TLB */
60 #define MMU_CFG_offTBW 8 /* TLB ways(non-associative) TBS */
61 #define MMU_CFG_offTBS 11 /* TLB sets per way(non-associative) TBS */
69 #define MMU_CFG_offNTPT 27 /* Partitions for non-translated attributes */
72 #define MMU_CFG_offNTME 30 /* Non-translated VA to PA mapping */
164 #define PSW_offWBNA 14 /* Write Back Non-Allocate */
249 #define ITYPE_offCPID 20 /* Co-Processor ID which generate the exception */
257 #define FPU_CPID 0 /* FPU Co-Processor ID is 0 */
300 #define MERR_offBUSERR 31 /* Bus error caused by a load insn */
331 #define INT_MASK_offIDIVZE 30 /* Enable detection for Divide-By-Zero */
375 #define MMU_CTL_offNTC0 1 /* Non-Translated Cachebility of partition 0 */
376 #define MMU_CTL_offNTC1 3 /* Non-Translated Cachebility of partition 1 */
377 #define MMU_CTL_offNTC2 5 /* Non-Translated Cachebility of partition 2 */
378 #define MMU_CTL_offNTC3 7 /* Non-Translated Cachebility of partition 3 */
379 #define MMU_CTL_offTBALCK 9 /* TLB all-lock resolution scheme */
381 #define MMU_CTL_offNTM0 11 /* Non-Translated VA to PA of partition 0 */
382 #define MMU_CTL_offNTM1 13 /* Non-Translated VA to PA of partition 1 */
383 #define MMU_CTL_offNTM2 15 /* Non-Translated VA to PA of partition 2 */
384 #define MMU_CTL_offNTM3 17 /* Non-Translated VA to PA of partition 3 */
457 #define TLB_MISC_offACC_PSZ 0 /* Page size of a PTE entry */
478 #define ILMB_offIEN 0 /* Enable ILM */
479 #define ILMB_offILMSZ 1 /* Size of ILM */
481 #define ILMB_offIBPA 20 /* Base PA of ILM */
492 #define DLMB_offDBM 5 /* Enable Double-Buffer Mode for DLM */
493 #define DLMB_offDBB 6 /* Double-buffer bank which can be accessed by the processor */
506 #define CACHE_CTL_offIC_EN 0 /* Enable I-cache */
507 #define CACHE_CTL_offDC_EN 1 /* Enable D-cache */
508 #define CACHE_CTL_offICALCK 2 /* I-cache all-lock resolution scheme */
509 #define CACHE_CTL_offDCALCK 3 /* D-cache all-lock resolution scheme */
510 #define CACHE_CTL_offDCCWF 4 /* Enable D-cache Critical Word Forwarding */
511 #define CACHE_CTL_offDCPMW 5 /* Enable D-cache concurrent miss and write-back processing */
543 * dr0+(n*5): BPCn (n=0-7) (Breakpoint Control Register)
547 #define BPC_offS 2 /* Data address comparison for a store instruction */
568 * dr1+(n*5): BPAn (n=0-7) (Breakpoint Address Register)
574 * dr2+(n*5): BPAMn (n=0-7) (Breakpoint Address Mask Register)
580 * dr3+(n*5): BPVn (n=0-7) Breakpoint Data Value Register
587 * dr4+(n*5): BPCIDn (n=0-7) (Breakpoint Context ID Register)
589 #define BPCID_offCID 0 /* CID that will be compared with a process's CID */
654 #define TECR_offBP 0 /* Controld which BP is used as a trigger source */
655 #define TECR_offNMI 8 /* Use NMI as a trigger source */
656 #define TECR_offHWINT 9 /* Corresponding interrupt is used as a trigger source */
657 #define TECR_offEVIC 15 /* Enable HWINT as a trigger source in EVIC mode */
658 #define TECR_offSYS 16 /* Enable SYSCALL instruction as a trigger source */
659 #define TECR_offDBG 17 /* Enable debug exception as a trigger source */
660 #define TECR_offMRE 18 /* Enable MMU related exception as a trigger source */
661 #define TECR_offE 19 /* An exception is used as a trigger source */
676 * pfr0-2: PFMC0-2 (Performance Counter Register 0-2)
726 #define SDZ_CTL_offICDZ 0 /* I-cache downsizing control */
727 #define SDZ_CTL_offDCDZ 3 /* D-cache downsizing control */
771 #define DMA_CFG_offUNEA 2 /* Un-aligned External Address transfer feature */
772 #define DMA_CFG_off2DET 3 /* 2-D Element Transfer feature */
823 #define DMA_SETUP_offUE 19 /* Enable the Un-aligned External Address */
824 #define DMA_SETUP_off2DE 20 /* Enable the 2-D External Transfer */
862 #define DMA_STATUS_offSTUNA 3 /* Un-aligned error on External Stride value */
864 #define DMA_STATUS_offEUNA 5 /* Un-aligned error on the External address */
865 #define DMA_STATUS_offIUNA 6 /* Un-aligned error on the Internal address */
866 #define DMA_STATUS_offIOOR 7 /* Out-Of-Range error on the Internal address */
883 #define DMA_2DSET_offWECNT 0 /* The Width Element Count for a 2-D region */
884 #define DMA_2DSET_offHTSTR 16 /* The Height Stride for a 2-D region */
892 #define DMA_2DSCTL_offSTWECNT 0 /* Startup Width Element Count for a 2-D region */
898 * fpcsr: FPCSR (Floating-Point Control Status Register)
945 * fpcfg: FPCFG (Floating-Point Configuration Register)