Lines Matching +full:imx8mm +full:- +full:noc

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright 2017-2018 NXP.
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <linux/clk-provider.h>
296 	struct device *dev = &pdev->dev;  in imx8mm_clocks_probe()
297 	struct device_node *np = dev->of_node;  in imx8mm_clocks_probe()
304 		return -ENOMEM;  in imx8mm_clocks_probe()
306 	clk_hw_data->num = IMX8MM_CLK_END;  in imx8mm_clocks_probe()
307 	hws = clk_hw_data->hws;  in imx8mm_clocks_probe()
317 	np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");  in imx8mm_clocks_probe()
321 		return -ENOMEM;  in imx8mm_clocks_probe()
405 	np = dev->of_node;  in imx8mm_clocks_probe()
448 	hws[IMX8MM_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc", imx8mm_noc_sels, base + 0x8d00);  in imx8mm_clocks_probe()
460 	 * DRAM clocks are manipulated from TF-A outside clock framework.  in imx8mm_clocks_probe()
605 					   hws[IMX8MM_CLK_A53_CORE]->clk,  in imx8mm_clocks_probe()
606 					   hws[IMX8MM_CLK_A53_CORE]->clk,  in imx8mm_clocks_probe()
607 					   hws[IMX8MM_ARM_PLL_OUT]->clk,  in imx8mm_clocks_probe()
608 					   hws[IMX8MM_CLK_A53_DIV]->clk);  in imx8mm_clocks_probe()
629 	{ .compatible = "fsl,imx8mm-ccm" },
637 		.name = "imx8mm-ccm",