55 static DEFINE_SPINLOCK(clk_lock);
189 				ARRAY_SIZE(uart_factor_tbl), &clk_lock);  in mmp2_clk_init()
194 				apbc_base + APBC_TWSI0, 10, 0, &clk_lock);  in mmp2_clk_init()
198 				apbc_base + APBC_TWSI1, 10, 0, &clk_lock);  in mmp2_clk_init()
202 				apbc_base + APBC_TWSI2, 10, 0, &clk_lock);  in mmp2_clk_init()
206 				apbc_base + APBC_TWSI3, 10, 0, &clk_lock);  in mmp2_clk_init()
210 				apbc_base + APBC_TWSI4, 10, 0, &clk_lock);  in mmp2_clk_init()
214 				apbc_base + APBC_TWSI5, 10, 0, &clk_lock);  in mmp2_clk_init()
218 				apbc_base + APBC_GPIO, 10, 0, &clk_lock);  in mmp2_clk_init()
222 				apbc_base + APBC_KPC, 10, 0, &clk_lock);  in mmp2_clk_init()
226 				apbc_base + APBC_RTC, 10, 0, &clk_lock);  in mmp2_clk_init()
230 				apbc_base + APBC_PWM0, 10, 0, &clk_lock);  in mmp2_clk_init()
234 				apbc_base + APBC_PWM1, 10, 0, &clk_lock);  in mmp2_clk_init()
238 				apbc_base + APBC_PWM2, 10, 0, &clk_lock);  in mmp2_clk_init()
242 				apbc_base + APBC_PWM3, 10, 0, &clk_lock);  in mmp2_clk_init()
248 				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
253 				apbc_base + APBC_UART0, 10, 0, &clk_lock);  in mmp2_clk_init()
259 				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
264 				apbc_base + APBC_UART1, 10, 0, &clk_lock);  in mmp2_clk_init()
270 				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
275 				apbc_base + APBC_UART2, 10, 0, &clk_lock);  in mmp2_clk_init()
281 				apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
286 				apbc_base + APBC_UART3, 10, 0, &clk_lock);  in mmp2_clk_init()
292 				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
296 				apbc_base + APBC_SSP0, 10, 0, &clk_lock);  in mmp2_clk_init()
302 				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
306 				apbc_base + APBC_SSP1, 10, 0, &clk_lock);  in mmp2_clk_init()
312 				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
316 				apbc_base + APBC_SSP2, 10, 0, &clk_lock);  in mmp2_clk_init()
322 				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);  in mmp2_clk_init()
326 				apbc_base + APBC_SSP3, 10, 0, &clk_lock);  in mmp2_clk_init()
332 				apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);  in mmp2_clk_init()
337 				10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);  in mmp2_clk_init()
341 				0x1b, &clk_lock);  in mmp2_clk_init()
345 				0x1b, &clk_lock);  in mmp2_clk_init()
349 				0x1b, &clk_lock);  in mmp2_clk_init()
353 				0x1b, &clk_lock);  in mmp2_clk_init()
357 				0x9, &clk_lock);  in mmp2_clk_init()
363 				apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
368 				8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);  in mmp2_clk_init()
372 				apmu_base + APMU_DISP0, 0x1b, &clk_lock);  in mmp2_clk_init()
376 				apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);  in mmp2_clk_init()
380 				apmu_base + APMU_DISP0, 0x1024, &clk_lock);  in mmp2_clk_init()
386 				apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
391 				8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);  in mmp2_clk_init()
395 				apmu_base + APMU_DISP1, 0x1b, &clk_lock);  in mmp2_clk_init()
399 				apmu_base + APMU_CCIC0, 0x1800, &clk_lock);  in mmp2_clk_init()
405 				apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
410 				17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);  in mmp2_clk_init()
414 				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);  in mmp2_clk_init()
418 				apmu_base + APMU_CCIC0, 0x24, &clk_lock);  in mmp2_clk_init()
423 				10, 5, 0, &clk_lock);  in mmp2_clk_init()
427 				apmu_base + APMU_CCIC0, 0x300, &clk_lock);  in mmp2_clk_init()
433 				apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
438 				16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);  in mmp2_clk_init()
442 				apmu_base + APMU_CCIC1, 0x1b, &clk_lock);  in mmp2_clk_init()
446 				apmu_base + APMU_CCIC1, 0x24, &clk_lock);  in mmp2_clk_init()
451 				10, 5, 0, &clk_lock);  in mmp2_clk_init()
455 				apmu_base + APMU_CCIC1, 0x300, &clk_lock);  in mmp2_clk_init()