48 static DEFINE_SPINLOCK(clk_lock);
160 				ARRAY_SIZE(uart_factor_tbl), &clk_lock);  in pxa168_clk_init()
165 				apbc_base + APBC_TWSI0, 10, 0, &clk_lock);  in pxa168_clk_init()
169 				apbc_base + APBC_TWSI1, 10, 0, &clk_lock);  in pxa168_clk_init()
173 				apbc_base + APBC_GPIO, 10, 0, &clk_lock);  in pxa168_clk_init()
177 				apbc_base + APBC_KPC, 10, 0, &clk_lock);  in pxa168_clk_init()
181 				apbc_base + APBC_RTC, 10, 0, &clk_lock);  in pxa168_clk_init()
185 				apbc_base + APBC_PWM0, 10, 0, &clk_lock);  in pxa168_clk_init()
189 				apbc_base + APBC_PWM1, 10, 0, &clk_lock);  in pxa168_clk_init()
193 				apbc_base + APBC_PWM2, 10, 0, &clk_lock);  in pxa168_clk_init()
197 				apbc_base + APBC_PWM3, 10, 0, &clk_lock);  in pxa168_clk_init()
203 				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
208 				apbc_base + APBC_UART0, 10, 0, &clk_lock);  in pxa168_clk_init()
214 				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
219 				apbc_base + APBC_UART1,	10, 0, &clk_lock);  in pxa168_clk_init()
225 				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
230 				apbc_base + APBC_UART2,	10, 0, &clk_lock);  in pxa168_clk_init()
236 				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
240 				10, 0, &clk_lock);  in pxa168_clk_init()
246 				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
250 				10, 0, &clk_lock);  in pxa168_clk_init()
256 				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
260 				10, 0, &clk_lock);  in pxa168_clk_init()
266 				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
270 				10, 0, &clk_lock);  in pxa168_clk_init()
276 				apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
280 				10, 0, &clk_lock);  in pxa168_clk_init()
284 				0x19b, &clk_lock);  in pxa168_clk_init()
290 				apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);  in pxa168_clk_init()
294 				0x1b, &clk_lock);  in pxa168_clk_init()
300 				apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);  in pxa168_clk_init()
304 				0x1b, &clk_lock);  in pxa168_clk_init()
308 				0x9, &clk_lock);  in pxa168_clk_init()
312 				0x12, &clk_lock);  in pxa168_clk_init()
318 				apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);  in pxa168_clk_init()
322 				apmu_base + APMU_DISP0, 0x1b, &clk_lock);  in pxa168_clk_init()
326 				apmu_base + APMU_DISP0, 0x24, &clk_lock);  in pxa168_clk_init()
332 				apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);  in pxa168_clk_init()
336 				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);  in pxa168_clk_init()
342 				apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);  in pxa168_clk_init()
346 				apmu_base + APMU_CCIC0, 0x24, &clk_lock);  in pxa168_clk_init()
351 				10, 5, 0, &clk_lock);  in pxa168_clk_init()
355 				apmu_base + APMU_CCIC0, 0x300, &clk_lock);  in pxa168_clk_init()