1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
24 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
37 	uint32_t source : 8; /* source index + 1 (0 == none) */  member
46 		/* For fixed-factor ones */
52 		/* for dual gate */
56 		} dual;  member
66 		.source = 1 + R9A06G032_##_src, .name = _n, \
70 		.source = 1 + R9A06G032_##_src, .name = _n, \
77 		.source = 1 + R9A06G032_##_src, .name = _n, \
81 		.source = 1 + R9A06G032_##_src, .name = _n, \
86 		.source = 1 + R9A06G032_##_src, .name = _n, \
87 		.dual = { .group = _g, .index = _gi, \
288 		.source = 1 + R9A06G032_DIV_UART,
290 		.dual.sel = ((0x34 / 4) << 5) | 30,
291 		.dual.group = 0,
297 		.source = 1 + R9A06G032_DIV_P2_PG,
299 		.dual.sel = ((0xec / 4) << 5) | 24,
300 		.dual.group = 1,
323 	u32 __iomem *reg = clocks->reg + (4 * (one >> 5));  in clk_rdesc_set()
334 	u32 __iomem *reg = clocks->reg + (4 * (one >> 5));  in clk_rdesc_get()
383 	struct device_node *np = dev->of_node;  in r9a06g032_attach_dev()
389 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++,  in r9a06g032_attach_dev()
391 		if (clkspec.np != pd->dev.of_node)  in r9a06g032_attach_dev()
415 	struct device_node *np = dev->of_node;  in r9a06g032_add_clk_domain()
420 		return -ENOMEM;  in r9a06g032_add_clk_domain()
422 	pd->name = np->name;  in r9a06g032_add_clk_domain()
423 	pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |  in r9a06g032_add_clk_domain()
425 	pd->attach_dev = r9a06g032_attach_dev;  in r9a06g032_add_clk_domain()
426 	pd->detach_dev = r9a06g032_detach_dev;  in r9a06g032_add_clk_domain()
439 	WARN_ON(!g->gate);  in r9a06g032_clk_gate_set()
441 	spin_lock_irqsave(&clocks->lock, flags);  in r9a06g032_clk_gate_set()
442 	clk_rdesc_set(clocks, g->gate, on);  in r9a06g032_clk_gate_set()
443 	/* De-assert reset */  in r9a06g032_clk_gate_set()
444 	if (g->reset)  in r9a06g032_clk_gate_set()
445 		clk_rdesc_set(clocks, g->reset, 1);  in r9a06g032_clk_gate_set()
446 	spin_unlock_irqrestore(&clocks->lock, flags);  in r9a06g032_clk_gate_set()
455 	if (g->ready || g->midle) {  in r9a06g032_clk_gate_set()
456 		spin_lock_irqsave(&clocks->lock, flags);  in r9a06g032_clk_gate_set()
457 		if (g->ready)  in r9a06g032_clk_gate_set()
458 			clk_rdesc_set(clocks, g->ready, on);  in r9a06g032_clk_gate_set()
460 		if (g->midle)  in r9a06g032_clk_gate_set()
461 			clk_rdesc_set(clocks, g->midle, !on);  in r9a06g032_clk_gate_set()
462 		spin_unlock_irqrestore(&clocks->lock, flags);  in r9a06g032_clk_gate_set()
471 	r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);  in r9a06g032_clk_gate_enable()
479 	r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);  in r9a06g032_clk_gate_disable()
487 	if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset))  in r9a06g032_clk_gate_is_enabled()
490 	return clk_rdesc_get(g->clocks, g->gate.gate);  in r9a06g032_clk_gate_is_enabled()
512 	init.name = desc->name;  in r9a06g032_register_gate()
518 	g->clocks = clocks;  in r9a06g032_register_gate()
519 	g->index = desc->index;  in r9a06g032_register_gate()
520 	g->gate = desc->gate;  in r9a06g032_register_gate()
521 	g->hw.init = &init;  in r9a06g032_register_gate()
528 	if (r9a06g032_clk_gate_is_enabled(&g->hw)) {  in r9a06g032_register_gate()
530 		pr_debug("%s was enabled, making read-only\n", desc->name);  in r9a06g032_register_gate()
533 	clk = clk_register(NULL, &g->hw);  in r9a06g032_register_gate()
559 	u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);  in r9a06g032_div_recalc_rate()
562 	if (div < clk->min)  in r9a06g032_div_recalc_rate()
563 		div = clk->min;  in r9a06g032_div_recalc_rate()
564 	else if (div > clk->max)  in r9a06g032_div_recalc_rate()
565 		div = clk->max;  in r9a06g032_div_recalc_rate()
583 	if (div <= clk->min)  in r9a06g032_div_clamp_div()
584 		return clk->min;  in r9a06g032_div_clamp_div()
585 	if (div >= clk->max)  in r9a06g032_div_clamp_div()
586 		return clk->max;  in r9a06g032_div_clamp_div()
588 	for (i = 0; clk->table_size && i < clk->table_size - 1; i++) {  in r9a06g032_div_clamp_div()
589 		if (div >= clk->table[i] && div <= clk->table[i + 1]) {  in r9a06g032_div_clamp_div()
590 			unsigned long m = rate -  in r9a06g032_div_clamp_div()
591 				DIV_ROUND_UP(prate, clk->table[i]);  in r9a06g032_div_clamp_div()
593 				DIV_ROUND_UP(prate, clk->table[i + 1]) -  in r9a06g032_div_clamp_div()
599 			div = p >= m ? clk->table[i] : clk->table[i + 1];  in r9a06g032_div_clamp_div()
614 		 hw->clk, rate, *prate, div);  in r9a06g032_div_round_rate()
616 		 clk->min, DIV_ROUND_UP(*prate, clk->min),  in r9a06g032_div_round_rate()
617 		clk->max, DIV_ROUND_UP(*prate, clk->max));  in r9a06g032_div_round_rate()
622 	 * that is 16 times the baud rate -- and that is wildly outside the  in r9a06g032_div_round_rate()
629 	if (clk->index == R9A06G032_DIV_UART ||  in r9a06g032_div_round_rate()
630 	    clk->index == R9A06G032_DIV_P2_PG) {  in r9a06g032_div_round_rate()
632 		return clk_get_rate(hw->clk);  in r9a06g032_div_round_rate()
634 	pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,  in r9a06g032_div_round_rate()
646 	u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);  in r9a06g032_div_set_rate()
648 	pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk,  in r9a06g032_div_set_rate()
683 	init.name = desc->name;  in r9a06g032_register_div()
689 	div->clocks = clocks;  in r9a06g032_register_div()
690 	div->index = desc->index;  in r9a06g032_register_div()
691 	div->reg = desc->reg;  in r9a06g032_register_div()
692 	div->hw.init = &init;  in r9a06g032_register_div()
693 	div->min = desc->div_min;  in r9a06g032_register_div()
694 	div->max = desc->div_max;  in r9a06g032_register_div()
696 	for (i = 0; i < ARRAY_SIZE(div->table) &&  in r9a06g032_register_div()
697 	     i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) {  in r9a06g032_register_div()
698 		div->table[div->table_size++] = desc->div_table[i];  in r9a06g032_register_div()
701 	clk = clk_register(NULL, &div->hw);  in r9a06g032_register_div()
711  * peripherals that have two potential clock source and two gates, one for
712  * each of the clock source - the used clock source (for all sub clocks)
714  * That single bit affects all sub-clocks, and therefore needs to change the
735 	return clk_rdesc_get(set->clocks, set->selector);  in r9a06g032_clk_mux_get_parent()
743 	clk_rdesc_set(set->clocks, set->selector, !!index);  in r9a06g032_clk_mux_set_parent()
771 	init.name = desc->name;  in r9a06g032_register_bitsel()
777 	g->clocks = clocks;  in r9a06g032_register_bitsel()
778 	g->index = desc->index;  in r9a06g032_register_bitsel()
779 	g->selector = desc->dual.sel;  in r9a06g032_register_bitsel()
780 	g->hw.init = &init;  in r9a06g032_register_bitsel()
782 	clk = clk_register(NULL, &g->hw);  in r9a06g032_register_bitsel()
804 	u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);  in r9a06g032_clk_dualgate_setenable()
807 	r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);  in r9a06g032_clk_dualgate_setenable()
808 	r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);  in r9a06g032_clk_dualgate_setenable()
832 	u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);  in r9a06g032_clk_dualgate_is_enabled()
834 	return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);  in r9a06g032_clk_dualgate_is_enabled()
857 	g->clocks = clocks;  in r9a06g032_register_dualgate()
858 	g->index = desc->index;  in r9a06g032_register_dualgate()
859 	g->selector = sel;  in r9a06g032_register_dualgate()
860 	g->gate[0].gate = desc->dual.g1;  in r9a06g032_register_dualgate()
861 	g->gate[0].reset = desc->dual.r1;  in r9a06g032_register_dualgate()
862 	g->gate[1].gate = desc->dual.g2;  in r9a06g032_register_dualgate()
863 	g->gate[1].reset = desc->dual.r2;  in r9a06g032_register_dualgate()
865 	init.name = desc->name;  in r9a06g032_register_dualgate()
870 	g->hw.init = &init;  in r9a06g032_register_dualgate()
876 	if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) {  in r9a06g032_register_dualgate()
878 		pr_debug("%s was enabled, making read-only\n", desc->name);  in r9a06g032_register_dualgate()
881 	clk = clk_register(NULL, &g->hw);  in r9a06g032_register_dualgate()
896 	struct device *dev = &pdev->dev;  in r9a06g032_clocks_probe()
897 	struct device_node *np = dev->of_node;  in r9a06g032_clocks_probe()
909 		return -ENOMEM;  in r9a06g032_clocks_probe()
911 	spin_lock_init(&clocks->lock);  in r9a06g032_clocks_probe()
913 	clocks->data.clks = clks;  in r9a06g032_clocks_probe()
914 	clocks->data.clk_num = R9A06G032_CLOCK_COUNT;  in r9a06g032_clocks_probe()
920 	clocks->reg = of_iomap(np, 0);  in r9a06g032_clocks_probe()
921 	if (WARN_ON(!clocks->reg))  in r9a06g032_clocks_probe()
922 		return -ENOMEM;  in r9a06g032_clocks_probe()
925 		const char *parent_name = d->source ?  in r9a06g032_clocks_probe()
926 			__clk_get_name(clocks->data.clks[d->source - 1]) :  in r9a06g032_clocks_probe()
930 		switch (d->type) {  in r9a06g032_clocks_probe()
932 			clk = clk_register_fixed_factor(NULL, d->name,  in r9a06g032_clocks_probe()
934 							d->mul, d->div);  in r9a06g032_clocks_probe()
944 			uart_group_sel[d->dual.group] = d->dual.sel;  in r9a06g032_clocks_probe()
950 							  uart_group_sel[d->dual.group]);  in r9a06g032_clocks_probe()
953 		clocks->data.clks[d->index] = clk;  in r9a06g032_clocks_probe()
955 	error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data);  in r9a06g032_clocks_probe()
968 	{ .compatible = "renesas,r9a06g032-sysctrl" },
974 		.name	= "renesas,r9a06g032-sysctrl",