Lines Matching +full:cpg +full:- +full:div6 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47 * R-Car Gen2, R-Car Gen3, and RZ/G1.
48 * These are NOT valid for R-Car Gen1 and RZ/A1!
104 #define RMSTPCR(i) (smstpcr[i] - 0x20)
122 * Clock Pulse Generator / Module Standby and Software Reset Private Data
125 * @dev: CPG/MSSR device
126 * @base: CPG/MSSR register block base address
127 * @reg_layout: CPG/MSSR register layout
129 * @np: Device node in DT for this CPG/MSSR module
132 * @last_dt_core_clk: ID of the last Core Clock exported to DT
133 * @notifiers: Notifier chain to save/restore clock state for system resume
172 * struct mstp_clock - MSTP gating clock
173 * @hw: handle between common and hardware-specific interfaces
174 * @index: MSTP clock number
175 * @priv: CPG/MSSR private data
187 struct mstp_clock *clock = to_mstp_clock(hw); in cpg_mstp_clock_endisable() local
188 struct cpg_mssr_priv *priv = clock->priv; in cpg_mstp_clock_endisable()
189 unsigned int reg = clock->index / 32; in cpg_mstp_clock_endisable()
190 unsigned int bit = clock->index % 32; in cpg_mstp_clock_endisable()
191 struct device *dev = priv->dev; in cpg_mstp_clock_endisable()
197 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, in cpg_mstp_clock_endisable()
199 spin_lock_irqsave(&priv->rmw_lock, flags); in cpg_mstp_clock_endisable()
201 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mstp_clock_endisable()
202 value = readb(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
207 writeb(value, priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
210 readb(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
211 barrier_data(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
213 value = readl(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
218 writel(value, priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
221 spin_unlock_irqrestore(&priv->rmw_lock, flags); in cpg_mstp_clock_endisable()
223 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_endisable()
226 for (i = 1000; i > 0; --i) { in cpg_mstp_clock_endisable()
227 if (!(readl(priv->base + priv->status_regs[reg]) & bitmask)) in cpg_mstp_clock_endisable()
234 priv->base + priv->control_regs[reg], bit); in cpg_mstp_clock_endisable()
235 return -ETIMEDOUT; in cpg_mstp_clock_endisable()
253 struct mstp_clock *clock = to_mstp_clock(hw); in cpg_mstp_clock_is_enabled() local
254 struct cpg_mssr_priv *priv = clock->priv; in cpg_mstp_clock_is_enabled()
257 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_is_enabled()
258 value = readb(priv->base + priv->control_regs[clock->index / 32]); in cpg_mstp_clock_is_enabled()
260 value = readl(priv->base + priv->status_regs[clock->index / 32]); in cpg_mstp_clock_is_enabled()
262 return !(value & BIT(clock->index % 32)); in cpg_mstp_clock_is_enabled()
275 unsigned int clkidx = clkspec->args[1]; in cpg_mssr_clk_src_twocell_get()
277 struct device *dev = priv->dev; in cpg_mssr_clk_src_twocell_get()
283 switch (clkspec->args[0]) { in cpg_mssr_clk_src_twocell_get()
286 if (clkidx > priv->last_dt_core_clk) { in cpg_mssr_clk_src_twocell_get()
287 dev_err(dev, "Invalid %s clock index %u\n", type, in cpg_mssr_clk_src_twocell_get()
289 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
291 clk = priv->clks[clkidx]; in cpg_mssr_clk_src_twocell_get()
296 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_clk_src_twocell_get()
298 range_check = 7 - (clkidx % 10); in cpg_mssr_clk_src_twocell_get()
301 range_check = 31 - (clkidx % 100); in cpg_mssr_clk_src_twocell_get()
303 if (range_check < 0 || idx >= priv->num_mod_clks) { in cpg_mssr_clk_src_twocell_get()
304 dev_err(dev, "Invalid %s clock index %u\n", type, in cpg_mssr_clk_src_twocell_get()
306 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
308 clk = priv->clks[priv->num_core_clks + idx]; in cpg_mssr_clk_src_twocell_get()
312 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); in cpg_mssr_clk_src_twocell_get()
313 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
317 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, in cpg_mssr_clk_src_twocell_get()
320 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", in cpg_mssr_clk_src_twocell_get()
321 clkspec->args[0], clkspec->args[1], clk, in cpg_mssr_clk_src_twocell_get()
330 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; in cpg_mssr_register_core_clk()
331 struct device *dev = priv->dev; in cpg_mssr_register_core_clk()
332 unsigned int id = core->id, div = core->div; in cpg_mssr_register_core_clk()
335 WARN_DEBUG(id >= priv->num_core_clks); in cpg_mssr_register_core_clk()
336 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); in cpg_mssr_register_core_clk()
338 if (!core->name) { in cpg_mssr_register_core_clk()
339 /* Skip NULLified clock */ in cpg_mssr_register_core_clk()
343 switch (core->type) { in cpg_mssr_register_core_clk()
345 clk = of_clk_get_by_name(priv->np, core->name); in cpg_mssr_register_core_clk()
351 WARN_DEBUG(core->parent >= priv->num_core_clks); in cpg_mssr_register_core_clk()
352 parent = priv->clks[core->parent]; in cpg_mssr_register_core_clk()
360 if (core->type == CLK_TYPE_DIV6_RO) in cpg_mssr_register_core_clk()
361 /* Multiply with the DIV6 register value */ in cpg_mssr_register_core_clk()
362 div *= (readl(priv->base + core->offset) & 0x3f) + 1; in cpg_mssr_register_core_clk()
364 if (core->type == CLK_TYPE_DIV6P1) { in cpg_mssr_register_core_clk()
365 clk = cpg_div6_register(core->name, 1, &parent_name, in cpg_mssr_register_core_clk()
366 priv->base + core->offset, in cpg_mssr_register_core_clk()
367 &priv->notifiers); in cpg_mssr_register_core_clk()
369 clk = clk_register_fixed_factor(NULL, core->name, in cpg_mssr_register_core_clk()
371 core->mult, div); in cpg_mssr_register_core_clk()
376 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, in cpg_mssr_register_core_clk()
377 core->mult); in cpg_mssr_register_core_clk()
381 if (info->cpg_clk_register) in cpg_mssr_register_core_clk()
382 clk = info->cpg_clk_register(dev, core, info, in cpg_mssr_register_core_clk()
383 priv->clks, priv->base, in cpg_mssr_register_core_clk()
384 &priv->notifiers); in cpg_mssr_register_core_clk()
386 dev_err(dev, "%s has unsupported core clock type %u\n", in cpg_mssr_register_core_clk()
387 core->name, core->type); in cpg_mssr_register_core_clk()
394 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); in cpg_mssr_register_core_clk()
395 priv->clks[id] = clk; in cpg_mssr_register_core_clk()
399 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", in cpg_mssr_register_core_clk()
400 core->name, PTR_ERR(clk)); in cpg_mssr_register_core_clk()
407 struct mstp_clock *clock = NULL; in cpg_mssr_register_mod_clk() local
408 struct device *dev = priv->dev; in cpg_mssr_register_mod_clk()
409 unsigned int id = mod->id; in cpg_mssr_register_mod_clk()
415 WARN_DEBUG(id < priv->num_core_clks); in cpg_mssr_register_mod_clk()
416 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); in cpg_mssr_register_mod_clk()
417 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); in cpg_mssr_register_mod_clk()
418 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); in cpg_mssr_register_mod_clk()
420 if (!mod->name) { in cpg_mssr_register_mod_clk()
421 /* Skip NULLified clock */ in cpg_mssr_register_mod_clk()
425 parent = priv->clks[mod->parent]; in cpg_mssr_register_mod_clk()
431 clock = kzalloc(sizeof(*clock), GFP_KERNEL); in cpg_mssr_register_mod_clk()
432 if (!clock) { in cpg_mssr_register_mod_clk()
433 clk = ERR_PTR(-ENOMEM); in cpg_mssr_register_mod_clk()
437 init.name = mod->name; in cpg_mssr_register_mod_clk()
444 clock->index = id - priv->num_core_clks; in cpg_mssr_register_mod_clk()
445 clock->priv = priv; in cpg_mssr_register_mod_clk()
446 clock->hw.init = &init; in cpg_mssr_register_mod_clk()
448 for (i = 0; i < info->num_crit_mod_clks; i++) in cpg_mssr_register_mod_clk()
449 if (id == info->crit_mod_clks[i] && in cpg_mssr_register_mod_clk()
450 cpg_mstp_clock_is_enabled(&clock->hw)) { in cpg_mssr_register_mod_clk()
452 mod->name); in cpg_mssr_register_mod_clk()
457 clk = clk_register(NULL, &clock->hw); in cpg_mssr_register_mod_clk()
461 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); in cpg_mssr_register_mod_clk()
462 priv->clks[id] = clk; in cpg_mssr_register_mod_clk()
463 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); in cpg_mssr_register_mod_clk()
467 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", in cpg_mssr_register_mod_clk()
468 mod->name, PTR_ERR(clk)); in cpg_mssr_register_mod_clk()
469 kfree(clock); in cpg_mssr_register_mod_clk()
485 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2) in cpg_mssr_is_pm_clk()
488 switch (clkspec->args[0]) { in cpg_mssr_is_pm_clk()
490 for (i = 0; i < pd->num_core_pm_clks; i++) in cpg_mssr_is_pm_clk()
491 if (clkspec->args[1] == pd->core_pm_clks[i]) in cpg_mssr_is_pm_clk()
506 struct device_node *np = dev->of_node; in cpg_mssr_attach_dev()
513 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); in cpg_mssr_attach_dev()
514 return -EPROBE_DEFER; in cpg_mssr_attach_dev()
517 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, in cpg_mssr_attach_dev()
562 struct device_node *np = dev->of_node; in cpg_mssr_add_clk_domain()
569 return -ENOMEM; in cpg_mssr_add_clk_domain()
571 pd->num_core_pm_clks = num_core_pm_clks; in cpg_mssr_add_clk_domain()
572 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); in cpg_mssr_add_clk_domain()
574 genpd = &pd->genpd; in cpg_mssr_add_clk_domain()
575 genpd->name = np->name; in cpg_mssr_add_clk_domain()
576 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | in cpg_mssr_add_clk_domain()
578 genpd->attach_dev = cpg_mssr_attach_dev; in cpg_mssr_add_clk_domain()
579 genpd->detach_dev = cpg_mssr_detach_dev; in cpg_mssr_add_clk_domain()
599 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); in cpg_mssr_reset()
602 writel(bitmask, priv->base + priv->reset_regs[reg]); in cpg_mssr_reset()
604 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ in cpg_mssr_reset()
608 writel(bitmask, priv->base + priv->reset_clear_regs[reg]); in cpg_mssr_reset()
620 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); in cpg_mssr_assert()
622 writel(bitmask, priv->base + priv->reset_regs[reg]); in cpg_mssr_assert()
634 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); in cpg_mssr_deassert()
636 writel(bitmask, priv->base + priv->reset_clear_regs[reg]); in cpg_mssr_deassert()
648 return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask); in cpg_mssr_status()
662 unsigned int unpacked = reset_spec->args[0]; in cpg_mssr_reset_xlate()
665 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { in cpg_mssr_reset_xlate()
666 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); in cpg_mssr_reset_xlate()
667 return -EINVAL; in cpg_mssr_reset_xlate()
675 priv->rcdev.ops = &cpg_mssr_reset_ops; in cpg_mssr_reset_controller_register()
676 priv->rcdev.of_node = priv->dev->of_node; in cpg_mssr_reset_controller_register()
677 priv->rcdev.of_reset_n_cells = 1; in cpg_mssr_reset_controller_register()
678 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; in cpg_mssr_reset_controller_register()
679 priv->rcdev.nr_resets = priv->num_mod_clks; in cpg_mssr_reset_controller_register()
680 return devm_reset_controller_register(priv->dev, &priv->rcdev); in cpg_mssr_reset_controller_register()
694 .compatible = "renesas,r7s9210-cpg-mssr",
700 .compatible = "renesas,r8a7742-cpg-mssr",
706 .compatible = "renesas,r8a7743-cpg-mssr",
711 .compatible = "renesas,r8a7744-cpg-mssr",
717 .compatible = "renesas,r8a7745-cpg-mssr",
723 .compatible = "renesas,r8a77470-cpg-mssr",
729 .compatible = "renesas,r8a774a1-cpg-mssr",
735 .compatible = "renesas,r8a774b1-cpg-mssr",
741 .compatible = "renesas,r8a774c0-cpg-mssr",
747 .compatible = "renesas,r8a774e1-cpg-mssr",
753 .compatible = "renesas,r8a7790-cpg-mssr",
759 .compatible = "renesas,r8a7791-cpg-mssr",
762 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
764 .compatible = "renesas,r8a7793-cpg-mssr",
770 .compatible = "renesas,r8a7792-cpg-mssr",
776 .compatible = "renesas,r8a7794-cpg-mssr",
782 .compatible = "renesas,r8a7795-cpg-mssr",
788 .compatible = "renesas,r8a7796-cpg-mssr",
794 .compatible = "renesas,r8a77961-cpg-mssr",
800 .compatible = "renesas,r8a77965-cpg-mssr",
806 .compatible = "renesas,r8a77970-cpg-mssr",
812 .compatible = "renesas,r8a77980-cpg-mssr",
818 .compatible = "renesas,r8a77990-cpg-mssr",
824 .compatible = "renesas,r8a77995-cpg-mssr",
830 .compatible = "renesas,r8a779a0-cpg-mssr",
853 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { in cpg_mssr_suspend_noirq()
854 if (priv->smstpcr_saved[reg].mask) in cpg_mssr_suspend_noirq()
855 priv->smstpcr_saved[reg].val = in cpg_mssr_suspend_noirq()
856 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? in cpg_mssr_suspend_noirq()
857 readb(priv->base + priv->control_regs[reg]) : in cpg_mssr_suspend_noirq()
858 readl(priv->base + priv->control_regs[reg]); in cpg_mssr_suspend_noirq()
862 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL); in cpg_mssr_suspend_noirq()
878 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL); in cpg_mssr_resume_noirq()
881 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { in cpg_mssr_resume_noirq()
882 mask = priv->smstpcr_saved[reg].mask; in cpg_mssr_resume_noirq()
886 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_resume_noirq()
887 oldval = readb(priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
889 oldval = readl(priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
891 newval |= priv->smstpcr_saved[reg].val & mask; in cpg_mssr_resume_noirq()
895 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_resume_noirq()
896 writeb(newval, priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
898 readb(priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
899 barrier_data(priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
902 writel(newval, priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
905 mask &= ~priv->smstpcr_saved[reg].val; in cpg_mssr_resume_noirq()
909 for (i = 1000; i > 0; --i) { in cpg_mssr_resume_noirq()
910 oldval = readl(priv->base + priv->status_regs[reg]); in cpg_mssr_resume_noirq()
918 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? in cpg_mssr_resume_noirq()
942 if (info->init) { in cpg_mssr_common_init()
943 error = info->init(dev); in cpg_mssr_common_init()
948 nclks = info->num_total_core_clks + info->num_hw_mod_clks; in cpg_mssr_common_init()
951 return -ENOMEM; in cpg_mssr_common_init()
953 priv->np = np; in cpg_mssr_common_init()
954 priv->dev = dev; in cpg_mssr_common_init()
955 spin_lock_init(&priv->rmw_lock); in cpg_mssr_common_init()
957 priv->base = of_iomap(np, 0); in cpg_mssr_common_init()
958 if (!priv->base) { in cpg_mssr_common_init()
959 error = -ENOMEM; in cpg_mssr_common_init()
964 priv->num_core_clks = info->num_total_core_clks; in cpg_mssr_common_init()
965 priv->num_mod_clks = info->num_hw_mod_clks; in cpg_mssr_common_init()
966 priv->last_dt_core_clk = info->last_dt_core_clk; in cpg_mssr_common_init()
967 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); in cpg_mssr_common_init()
968 priv->reg_layout = info->reg_layout; in cpg_mssr_common_init()
969 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { in cpg_mssr_common_init()
970 priv->status_regs = mstpsr; in cpg_mssr_common_init()
971 priv->control_regs = smstpcr; in cpg_mssr_common_init()
972 priv->reset_regs = srcr; in cpg_mssr_common_init()
973 priv->reset_clear_regs = srstclr; in cpg_mssr_common_init()
974 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_common_init()
975 priv->control_regs = stbcr; in cpg_mssr_common_init()
976 } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) { in cpg_mssr_common_init()
977 priv->status_regs = mstpsr_for_v3u; in cpg_mssr_common_init()
978 priv->control_regs = mstpcr_for_v3u; in cpg_mssr_common_init()
979 priv->reset_regs = srcr_for_v3u; in cpg_mssr_common_init()
980 priv->reset_clear_regs = srstclr_for_v3u; in cpg_mssr_common_init()
982 error = -EINVAL; in cpg_mssr_common_init()
987 priv->clks[i] = ERR_PTR(-ENOENT); in cpg_mssr_common_init()
996 if (priv->base) in cpg_mssr_common_init()
997 iounmap(priv->base); in cpg_mssr_common_init()
1013 for (i = 0; i < info->num_early_core_clks; i++) in cpg_mssr_early_init()
1014 cpg_mssr_register_core_clk(&info->early_core_clks[i], info, in cpg_mssr_early_init()
1017 for (i = 0; i < info->num_early_mod_clks; i++) in cpg_mssr_early_init()
1018 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info, in cpg_mssr_early_init()
1025 struct device *dev = &pdev->dev; in cpg_mssr_probe()
1026 struct device_node *np = dev->of_node; in cpg_mssr_probe()
1035 error = cpg_mssr_common_init(dev, dev->of_node, info); in cpg_mssr_probe()
1041 priv->dev = dev; in cpg_mssr_probe()
1044 for (i = 0; i < info->num_core_clks; i++) in cpg_mssr_probe()
1045 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); in cpg_mssr_probe()
1047 for (i = 0; i < info->num_mod_clks; i++) in cpg_mssr_probe()
1048 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); in cpg_mssr_probe()
1056 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, in cpg_mssr_probe()
1057 info->num_core_pm_clks); in cpg_mssr_probe()
1062 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_probe()
1074 .name = "renesas-cpg-mssr",
1127 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");