Lines Matching +full:cpg +full:- +full:div6 +full:- +full:clock
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
12 * Definitions of CPG Core Clocks
15 * - Clock outputs exported to DT
16 * - External input clocks
17 * - Internal CPG clocks
34 CLK_TYPE_IN, /* External Clock Input */
35 CLK_TYPE_FF, /* Fixed Factor Clock */
36 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
37 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
38 CLK_TYPE_FR, /* Fixed Rate Clock */
70 /* Convert from sparse base-100 to packed index space */
71 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
78 /* Convert from sparse base-10 to packed index space */
95 * SoC-specific CPG/MSSR Description
97 * @early_core_clks: Array of Early Core Clock definitions
99 * @early_mod_clks: Array of Early Module Clock definitions
102 * @core_clks: Array of Core Clock definitions
104 * @last_dt_core_clk: ID of the last Core Clock exported to DT
107 * @mod_clks: Array of Module Clock definitions
111 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
114 * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
120 * @init: Optional callback to perform SoC-specific initialization
121 * @cpg_clk_register: Optional callback to handle special Core Clock types
186 * Helpers for fixing up clock tables depending on SoC revision