24 	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);  in socfpga_gate_clk_recalc_rate()  local
27 	if (socfpgaclk->fixed_div)  in socfpga_gate_clk_recalc_rate()
28 		div = socfpgaclk->fixed_div;  in socfpga_gate_clk_recalc_rate()
29 	else if (socfpgaclk->div_reg) {  in socfpga_gate_clk_recalc_rate()
30 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;  in socfpga_gate_clk_recalc_rate()
31 		val &= GENMASK(socfpgaclk->width - 1, 0);  in socfpga_gate_clk_recalc_rate()
40 	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);  in socfpga_clk_prepare()  local
45 	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {  in socfpga_clk_prepare()
47 			switch (socfpgaclk->clk_phase[i]) {  in socfpga_clk_prepare()
79 		if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))  in socfpga_clk_prepare()
80 			regmap_write(socfpgaclk->sys_mgr_base_addr,  in socfpga_clk_prepare()