170 	clk = of_clk_get(node, 0);  in _register_dpll()
233 	parent_name = of_clk_get_parent_name(node, 0);  in _register_dpll_x2()
258 		if (ret <= 0) {  in _register_dpll_x2()
260 		} else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {  in _register_dpll_x2()
293 	u8 dpll_mode = 0;  in of_ti_dpll_setup()
322 	if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))  in of_ti_dpll_setup()
395 		.idlest_mask = 0x1,  in of_ti_omap3_dpll_setup()
396 		.enable_mask = 0x7,  in of_ti_omap3_dpll_setup()
397 		.autoidle_mask = 0x7,  in of_ti_omap3_dpll_setup()
398 		.mult_mask = 0x7ff << 8,  in of_ti_omap3_dpll_setup()
399 		.div1_mask = 0x7f,  in of_ti_omap3_dpll_setup()
403 		.freqsel_mask = 0xf0,  in of_ti_omap3_dpll_setup()
420 		.idlest_mask = 0x1,  in of_ti_omap3_core_dpll_setup()
421 		.enable_mask = 0x7,  in of_ti_omap3_core_dpll_setup()
422 		.autoidle_mask = 0x7,  in of_ti_omap3_core_dpll_setup()
423 		.mult_mask = 0x7ff << 16,  in of_ti_omap3_core_dpll_setup()
424 		.div1_mask = 0x7f << 8,  in of_ti_omap3_core_dpll_setup()
428 		.freqsel_mask = 0xf0,  in of_ti_omap3_core_dpll_setup()
439 		.idlest_mask = 0x1 << 1,  in of_ti_omap3_per_dpll_setup()
440 		.enable_mask = 0x7 << 16,  in of_ti_omap3_per_dpll_setup()
441 		.autoidle_mask = 0x7 << 3,  in of_ti_omap3_per_dpll_setup()
442 		.mult_mask = 0x7ff << 8,  in of_ti_omap3_per_dpll_setup()
443 		.div1_mask = 0x7f,  in of_ti_omap3_per_dpll_setup()
447 		.freqsel_mask = 0xf00000,  in of_ti_omap3_per_dpll_setup()
459 		.idlest_mask = 0x1 << 1,  in of_ti_omap3_per_jtype_dpll_setup()
460 		.enable_mask = 0x7 << 16,  in of_ti_omap3_per_jtype_dpll_setup()
461 		.autoidle_mask = 0x7 << 3,  in of_ti_omap3_per_jtype_dpll_setup()
462 		.mult_mask = 0xfff << 8,  in of_ti_omap3_per_jtype_dpll_setup()
463 		.div1_mask = 0x7f,  in of_ti_omap3_per_jtype_dpll_setup()
467 		.sddiv_mask = 0xff << 24,  in of_ti_omap3_per_jtype_dpll_setup()
468 		.dco_mask = 0xe << 20,  in of_ti_omap3_per_jtype_dpll_setup()
482 		.idlest_mask = 0x1,  in of_ti_omap4_dpll_setup()
483 		.enable_mask = 0x7,  in of_ti_omap4_dpll_setup()
484 		.autoidle_mask = 0x7,  in of_ti_omap4_dpll_setup()
485 		.mult_mask = 0x7ff << 8,  in of_ti_omap4_dpll_setup()
486 		.div1_mask = 0x7f,  in of_ti_omap4_dpll_setup()
501 		.idlest_mask = 0x1,  in of_ti_omap5_mpu_dpll_setup()
502 		.enable_mask = 0x7,  in of_ti_omap5_mpu_dpll_setup()
503 		.autoidle_mask = 0x7,  in of_ti_omap5_mpu_dpll_setup()
504 		.mult_mask = 0x7ff << 8,  in of_ti_omap5_mpu_dpll_setup()
505 		.div1_mask = 0x7f,  in of_ti_omap5_mpu_dpll_setup()
522 		.idlest_mask = 0x1,  in of_ti_omap4_core_dpll_setup()
523 		.enable_mask = 0x7,  in of_ti_omap4_core_dpll_setup()
524 		.autoidle_mask = 0x7,  in of_ti_omap4_core_dpll_setup()
525 		.mult_mask = 0x7ff << 8,  in of_ti_omap4_core_dpll_setup()
526 		.div1_mask = 0x7f,  in of_ti_omap4_core_dpll_setup()
543 		.idlest_mask = 0x1,  in of_ti_omap4_m4xen_dpll_setup()
544 		.enable_mask = 0x7,  in of_ti_omap4_m4xen_dpll_setup()
545 		.autoidle_mask = 0x7,  in of_ti_omap4_m4xen_dpll_setup()
546 		.mult_mask = 0x7ff << 8,  in of_ti_omap4_m4xen_dpll_setup()
547 		.div1_mask = 0x7f,  in of_ti_omap4_m4xen_dpll_setup()
551 		.m4xen_mask = 0x800,  in of_ti_omap4_m4xen_dpll_setup()
564 		.idlest_mask = 0x1,  in of_ti_omap4_jtype_dpll_setup()
565 		.enable_mask = 0x7,  in of_ti_omap4_jtype_dpll_setup()
566 		.autoidle_mask = 0x7,  in of_ti_omap4_jtype_dpll_setup()
567 		.mult_mask = 0xfff << 8,  in of_ti_omap4_jtype_dpll_setup()
568 		.div1_mask = 0xff,  in of_ti_omap4_jtype_dpll_setup()
572 		.sddiv_mask = 0xff << 24,  in of_ti_omap4_jtype_dpll_setup()
586 		.idlest_mask = 0x1,  in of_ti_am3_no_gate_dpll_setup()
587 		.enable_mask = 0x7,  in of_ti_am3_no_gate_dpll_setup()
588 		.mult_mask = 0x7ff << 8,  in of_ti_am3_no_gate_dpll_setup()
589 		.div1_mask = 0x7f,  in of_ti_am3_no_gate_dpll_setup()
605 		.idlest_mask = 0x1,  in of_ti_am3_jtype_dpll_setup()
606 		.enable_mask = 0x7,  in of_ti_am3_jtype_dpll_setup()
607 		.mult_mask = 0x7ff << 8,  in of_ti_am3_jtype_dpll_setup()
608 		.div1_mask = 0x7f,  in of_ti_am3_jtype_dpll_setup()
625 		.idlest_mask = 0x1,  in of_ti_am3_no_gate_jtype_dpll_setup()
626 		.enable_mask = 0x7,  in of_ti_am3_no_gate_jtype_dpll_setup()
627 		.mult_mask = 0x7ff << 8,  in of_ti_am3_no_gate_jtype_dpll_setup()
628 		.div1_mask = 0x7f,  in of_ti_am3_no_gate_jtype_dpll_setup()
646 		.idlest_mask = 0x1,  in of_ti_am3_dpll_setup()
647 		.enable_mask = 0x7,  in of_ti_am3_dpll_setup()
648 		.mult_mask = 0x7ff << 8,  in of_ti_am3_dpll_setup()
649 		.div1_mask = 0x7f,  in of_ti_am3_dpll_setup()
664 		.idlest_mask = 0x1,  in of_ti_am3_core_dpll_setup()
665 		.enable_mask = 0x7,  in of_ti_am3_core_dpll_setup()
666 		.mult_mask = 0x7ff << 8,  in of_ti_am3_core_dpll_setup()
667 		.div1_mask = 0x7f,  in of_ti_am3_core_dpll_setup()
683 		.enable_mask = 0x3,  in of_ti_omap2_core_dpll_setup()
684 		.mult_mask = 0x3ff << 12,  in of_ti_omap2_core_dpll_setup()
685 		.div1_mask = 0xf << 8,  in of_ti_omap2_core_dpll_setup()