Lines Matching +full:- +full:clint

1 # SPDX-License-Identifier: GPL-2.0-only
165 	  Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
188 	  32-bit free running decrementing counters.
242 	bool "Integrator-AP timer driver" if COMPILE_TEST
245 	  Enables support for the Integrator-AP timer.
278 	  available on many OMAP-like platforms.
287 	  It has a 64-bit counter with update rate up to 1000MHz.
288 	  This counter is accessed via couple of 32-bit memory-mapped registers.
307 	bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
311 	  These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
316 	bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
320 	  This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP).
338 	  power-of-2 divisor of the clock rate. The behaviour can also be
341 	  The main use of the event stream is wfe-based timeouts of userspace
352 	bool "Workaround for Freescale/NXP Erratum A-008585"
358 	  A-008585 ("ARM generic timer may contain an erroneous
360 	  fsl,erratum-a008585 property is found in the timer node.
369 	  161010101. The workaround will be active if the hisilicon,erratum-161010101
373 	bool "Workaround for Cortex-A73 erratum 858921"
378 	  This option enables a workaround applicable to Cortex-A73
391 	  allwinner,erratum-unknown1 property is found in the timer node.
507 	bool "J-Core PIT timer driver" if COMPILE_TEST
513 	  the integrated PIT in the J-Core synthesizable, open source SoC.
521 	  the Compare Match Timer (CMT) hardware available in 16/32/48-bit
529 	  This enables build of a clockevent driver for the Multi-Function
531 	  This hardware comes with 16-bit timer registers.
546 	  the 32-bit Timer Unit (TMU) hardware available on a wide range
555 	  the 48-bit System Timer (STI) hardware available on a SoCs
591 	bool "Clocksource for PXA or SA-11x0 platform" if COMPILE_TEST
595 	  This enables OST0 support available on PXA and SA-11x0
658 	bool "Timer for the RISC-V platform" if COMPILE_TEST
663 	  This enables the per-hart timer built into all RISC-V systems, which
665 	  required for all RISC-V systems.
668 	bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
673 	  This option enables the CLINT timer for RISC-V systems.  The CLINT
674 	  driver is usually used for NoMMU RISC-V systems.
677 	bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
681 	  Say yes here to enable C-SKY SMP timer driver used for C-SKY SMP