54 	{0, SPEEDSTEP_HIGH,	0},
55 	{0, SPEEDSTEP_LOW,	0},
56 	{0, 0,			CPUFREQ_TABLE_END},
71 	pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);  in speedstep_find_register()
72 	if (!(pmbase & 0x01)) {  in speedstep_find_register()
77 	pmbase &= 0xFFFFFFFE;  in speedstep_find_register()
83 	pr_debug("pmbase is 0x%x\n", pmbase);  in speedstep_find_register()
84 	return 0;  in speedstep_find_register()
100 	if (state > 0x1)  in speedstep_set_state()
107 	value = inb(pmbase + 0x50);  in speedstep_set_state()
109 	pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);  in speedstep_set_state()
112 	value &= 0xFE;  in speedstep_set_state()
115 	pr_debug("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);  in speedstep_set_state()
118 	pm2_blk = inb(pmbase + 0x20);  in speedstep_set_state()
119 	pm2_blk |= 0x01;  in speedstep_set_state()
120 	outb(pm2_blk, (pmbase + 0x20));  in speedstep_set_state()
123 	outb(value, (pmbase + 0x50));  in speedstep_set_state()
126 	pm2_blk &= 0xfe;  in speedstep_set_state()
127 	outb(pm2_blk, (pmbase + 0x20));  in speedstep_set_state()
130 	value = inb(pmbase + 0x50);  in speedstep_set_state()
135 	pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);  in speedstep_set_state()
137 	if (state == (value & 0x1))  in speedstep_set_state()
160 	u16 value = 0;  in speedstep_activate()
165 	pci_read_config_word(speedstep_chipset_dev, 0x00A0, &value);  in speedstep_activate()
166 	if (!(value & 0x08)) {  in speedstep_activate()
167 		value |= 0x08;  in speedstep_activate()
169 		pci_write_config_word(speedstep_chipset_dev, 0x00A0, value);  in speedstep_activate()
172 	return 0;  in speedstep_activate()
224 			return 0;  in speedstep_detect_chipset()
231 	return 0;  in speedstep_detect_chipset()
268 	return 0;  in speedstep_target()
308 	return 0;  in speedstep_cpu_init()
322 	X86_MATCH_VENDOR_FAM_MODEL(INTEL,  6, 0x8, 0),
323 	X86_MATCH_VENDOR_FAM_MODEL(INTEL,  6, 0xb, 0),
324 	X86_MATCH_VENDOR_FAM_MODEL(INTEL, 15, 0x2, 0),