Lines Matching refs:chan
447 void (*start_transfer)(struct xilinx_dma_chan *chan);
448 int (*stop_transfer)(struct xilinx_dma_chan *chan);
501 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE]; member
517 #define to_xilinx_chan(chan) \ argument
518 container_of(chan, struct xilinx_dma_chan, common)
521 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ argument
522 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
526 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) in dma_read() argument
528 return ioread32(chan->xdev->regs + reg); in dma_read()
531 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) in dma_write() argument
533 iowrite32(value, chan->xdev->regs + reg); in dma_write()
536 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg, in vdma_desc_write() argument
539 dma_write(chan, chan->desc_offset + reg, value); in vdma_desc_write()
542 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) in dma_ctrl_read() argument
544 return dma_read(chan, chan->ctrl_offset + reg); in dma_ctrl_read()
547 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg, in dma_ctrl_write() argument
550 dma_write(chan, chan->ctrl_offset + reg, value); in dma_ctrl_write()
553 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg, in dma_ctrl_clr() argument
556 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); in dma_ctrl_clr()
559 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg, in dma_ctrl_set() argument
562 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set); in dma_ctrl_set()
576 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg, in vdma_desc_write_64() argument
580 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); in vdma_desc_write_64()
583 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4); in vdma_desc_write_64()
586 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value) in dma_writeq() argument
588 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg); in dma_writeq()
591 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg, in xilinx_write() argument
594 if (chan->ext_addr) in xilinx_write()
595 dma_writeq(chan, reg, addr); in xilinx_write()
597 dma_ctrl_write(chan, reg, addr); in xilinx_write()
600 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan, in xilinx_axidma_buf() argument
605 if (chan->ext_addr) { in xilinx_axidma_buf()
614 static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, in xilinx_aximcdma_buf() argument
618 if (chan->ext_addr) { in xilinx_aximcdma_buf()
637 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan) in xilinx_vdma_alloc_tx_segment() argument
642 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); in xilinx_vdma_alloc_tx_segment()
658 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan) in xilinx_cdma_alloc_tx_segment() argument
663 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); in xilinx_cdma_alloc_tx_segment()
679 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan) in xilinx_axidma_alloc_tx_segment() argument
684 spin_lock_irqsave(&chan->lock, flags); in xilinx_axidma_alloc_tx_segment()
685 if (!list_empty(&chan->free_seg_list)) { in xilinx_axidma_alloc_tx_segment()
686 segment = list_first_entry(&chan->free_seg_list, in xilinx_axidma_alloc_tx_segment()
691 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_axidma_alloc_tx_segment()
694 dev_dbg(chan->dev, "Could not find free tx segment\n"); in xilinx_axidma_alloc_tx_segment()
706 xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan) in xilinx_aximcdma_alloc_tx_segment() argument
711 spin_lock_irqsave(&chan->lock, flags); in xilinx_aximcdma_alloc_tx_segment()
712 if (!list_empty(&chan->free_seg_list)) { in xilinx_aximcdma_alloc_tx_segment()
713 segment = list_first_entry(&chan->free_seg_list, in xilinx_aximcdma_alloc_tx_segment()
718 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_aximcdma_alloc_tx_segment()
750 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan, in xilinx_dma_free_tx_segment() argument
755 list_add_tail(&segment->node, &chan->free_seg_list); in xilinx_dma_free_tx_segment()
763 static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan, in xilinx_mcdma_free_tx_segment() argument
769 list_add_tail(&segment->node, &chan->free_seg_list); in xilinx_mcdma_free_tx_segment()
777 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan, in xilinx_cdma_free_tx_segment() argument
780 dma_pool_free(chan->desc_pool, segment, segment->phys); in xilinx_cdma_free_tx_segment()
788 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan, in xilinx_vdma_free_tx_segment() argument
791 dma_pool_free(chan->desc_pool, segment, segment->phys); in xilinx_vdma_free_tx_segment()
801 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan) in xilinx_dma_alloc_tx_descriptor() argument
820 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, in xilinx_dma_free_tx_descriptor() argument
831 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in xilinx_dma_free_tx_descriptor()
834 xilinx_vdma_free_tx_segment(chan, segment); in xilinx_dma_free_tx_descriptor()
836 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_free_tx_descriptor()
840 xilinx_cdma_free_tx_segment(chan, cdma_segment); in xilinx_dma_free_tx_descriptor()
842 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_free_tx_descriptor()
846 xilinx_dma_free_tx_segment(chan, axidma_segment); in xilinx_dma_free_tx_descriptor()
852 xilinx_mcdma_free_tx_segment(chan, aximcdma_segment); in xilinx_dma_free_tx_descriptor()
866 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan, in xilinx_dma_free_desc_list() argument
873 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_dma_free_desc_list()
881 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan) in xilinx_dma_free_descriptors() argument
885 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_free_descriptors()
887 xilinx_dma_free_desc_list(chan, &chan->pending_list); in xilinx_dma_free_descriptors()
888 xilinx_dma_free_desc_list(chan, &chan->done_list); in xilinx_dma_free_descriptors()
889 xilinx_dma_free_desc_list(chan, &chan->active_list); in xilinx_dma_free_descriptors()
891 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_free_descriptors()
900 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_free_chan_resources() local
903 dev_dbg(chan->dev, "Free all channel resources.\n"); in xilinx_dma_free_chan_resources()
905 xilinx_dma_free_descriptors(chan); in xilinx_dma_free_chan_resources()
907 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_free_chan_resources()
908 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_free_chan_resources()
909 INIT_LIST_HEAD(&chan->free_seg_list); in xilinx_dma_free_chan_resources()
910 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_free_chan_resources()
913 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * in xilinx_dma_free_chan_resources()
914 XILINX_DMA_NUM_DESCS, chan->seg_v, in xilinx_dma_free_chan_resources()
915 chan->seg_p); in xilinx_dma_free_chan_resources()
918 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v), in xilinx_dma_free_chan_resources()
919 chan->cyclic_seg_v, chan->cyclic_seg_p); in xilinx_dma_free_chan_resources()
922 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_free_chan_resources()
923 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_free_chan_resources()
924 INIT_LIST_HEAD(&chan->free_seg_list); in xilinx_dma_free_chan_resources()
925 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_free_chan_resources()
928 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) * in xilinx_dma_free_chan_resources()
929 XILINX_DMA_NUM_DESCS, chan->seg_mv, in xilinx_dma_free_chan_resources()
930 chan->seg_p); in xilinx_dma_free_chan_resources()
933 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA && in xilinx_dma_free_chan_resources()
934 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) { in xilinx_dma_free_chan_resources()
935 dma_pool_destroy(chan->desc_pool); in xilinx_dma_free_chan_resources()
936 chan->desc_pool = NULL; in xilinx_dma_free_chan_resources()
948 static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan, in xilinx_dma_get_residue() argument
961 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_get_residue()
967 chan->xdev->max_buffer_len; in xilinx_dma_get_residue()
968 } else if (chan->xdev->dma_config->dmatype == in xilinx_dma_get_residue()
975 chan->xdev->max_buffer_len; in xilinx_dma_get_residue()
984 chan->xdev->max_buffer_len; in xilinx_dma_get_residue()
997 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan, in xilinx_dma_chan_handle_cyclic() argument
1007 spin_unlock_irqrestore(&chan->lock, *flags); in xilinx_dma_chan_handle_cyclic()
1009 spin_lock_irqsave(&chan->lock, *flags); in xilinx_dma_chan_handle_cyclic()
1017 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan) in xilinx_dma_chan_desc_cleanup() argument
1022 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1024 list_for_each_entry_safe(desc, next, &chan->done_list, node) { in xilinx_dma_chan_desc_cleanup()
1028 xilinx_dma_chan_handle_cyclic(chan, desc, &flags); in xilinx_dma_chan_desc_cleanup()
1036 if (chan->direction == DMA_DEV_TO_MEM) in xilinx_dma_chan_desc_cleanup()
1047 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1049 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1053 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_dma_chan_desc_cleanup()
1059 if (chan->terminating) in xilinx_dma_chan_desc_cleanup()
1063 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1072 struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet); in xilinx_dma_do_tasklet() local
1074 xilinx_dma_chan_desc_cleanup(chan); in xilinx_dma_do_tasklet()
1085 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_alloc_chan_resources() local
1089 if (chan->desc_pool) in xilinx_dma_alloc_chan_resources()
1096 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_alloc_chan_resources()
1098 chan->seg_v = dma_alloc_coherent(chan->dev, in xilinx_dma_alloc_chan_resources()
1099 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS, in xilinx_dma_alloc_chan_resources()
1100 &chan->seg_p, GFP_KERNEL); in xilinx_dma_alloc_chan_resources()
1101 if (!chan->seg_v) { in xilinx_dma_alloc_chan_resources()
1102 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1104 chan->id); in xilinx_dma_alloc_chan_resources()
1113 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev, in xilinx_dma_alloc_chan_resources()
1114 sizeof(*chan->cyclic_seg_v), in xilinx_dma_alloc_chan_resources()
1115 &chan->cyclic_seg_p, in xilinx_dma_alloc_chan_resources()
1117 if (!chan->cyclic_seg_v) { in xilinx_dma_alloc_chan_resources()
1118 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1120 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * in xilinx_dma_alloc_chan_resources()
1121 XILINX_DMA_NUM_DESCS, chan->seg_v, in xilinx_dma_alloc_chan_resources()
1122 chan->seg_p); in xilinx_dma_alloc_chan_resources()
1125 chan->cyclic_seg_v->phys = chan->cyclic_seg_p; in xilinx_dma_alloc_chan_resources()
1128 chan->seg_v[i].hw.next_desc = in xilinx_dma_alloc_chan_resources()
1129 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) * in xilinx_dma_alloc_chan_resources()
1131 chan->seg_v[i].hw.next_desc_msb = in xilinx_dma_alloc_chan_resources()
1132 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) * in xilinx_dma_alloc_chan_resources()
1134 chan->seg_v[i].phys = chan->seg_p + in xilinx_dma_alloc_chan_resources()
1135 sizeof(*chan->seg_v) * i; in xilinx_dma_alloc_chan_resources()
1136 list_add_tail(&chan->seg_v[i].node, in xilinx_dma_alloc_chan_resources()
1137 &chan->free_seg_list); in xilinx_dma_alloc_chan_resources()
1139 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_alloc_chan_resources()
1141 chan->seg_mv = dma_alloc_coherent(chan->dev, in xilinx_dma_alloc_chan_resources()
1142 sizeof(*chan->seg_mv) * in xilinx_dma_alloc_chan_resources()
1144 &chan->seg_p, GFP_KERNEL); in xilinx_dma_alloc_chan_resources()
1145 if (!chan->seg_mv) { in xilinx_dma_alloc_chan_resources()
1146 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1148 chan->id); in xilinx_dma_alloc_chan_resources()
1152 chan->seg_mv[i].hw.next_desc = in xilinx_dma_alloc_chan_resources()
1153 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * in xilinx_dma_alloc_chan_resources()
1155 chan->seg_mv[i].hw.next_desc_msb = in xilinx_dma_alloc_chan_resources()
1156 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * in xilinx_dma_alloc_chan_resources()
1158 chan->seg_mv[i].phys = chan->seg_p + in xilinx_dma_alloc_chan_resources()
1159 sizeof(*chan->seg_mv) * i; in xilinx_dma_alloc_chan_resources()
1160 list_add_tail(&chan->seg_mv[i].node, in xilinx_dma_alloc_chan_resources()
1161 &chan->free_seg_list); in xilinx_dma_alloc_chan_resources()
1163 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_alloc_chan_resources()
1164 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", in xilinx_dma_alloc_chan_resources()
1165 chan->dev, in xilinx_dma_alloc_chan_resources()
1170 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool", in xilinx_dma_alloc_chan_resources()
1171 chan->dev, in xilinx_dma_alloc_chan_resources()
1177 if (!chan->desc_pool && in xilinx_dma_alloc_chan_resources()
1178 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) && in xilinx_dma_alloc_chan_resources()
1179 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) { in xilinx_dma_alloc_chan_resources()
1180 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1182 chan->id); in xilinx_dma_alloc_chan_resources()
1188 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_alloc_chan_resources()
1192 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, in xilinx_dma_alloc_chan_resources()
1196 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) in xilinx_dma_alloc_chan_resources()
1197 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, in xilinx_dma_alloc_chan_resources()
1211 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, in xilinx_dma_calc_copysize() argument
1217 chan->xdev->max_buffer_len); in xilinx_dma_calc_copysize()
1220 chan->xdev->common.copy_align) { in xilinx_dma_calc_copysize()
1226 (1 << chan->xdev->common.copy_align)); in xilinx_dma_calc_copysize()
1243 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_tx_status() local
1253 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_tx_status()
1254 if (!list_empty(&chan->active_list)) { in xilinx_dma_tx_status()
1255 desc = list_last_entry(&chan->active_list, in xilinx_dma_tx_status()
1261 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA) in xilinx_dma_tx_status()
1262 residue = xilinx_dma_get_residue(chan, desc); in xilinx_dma_tx_status()
1264 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_tx_status()
1277 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan) in xilinx_dma_stop_transfer() argument
1281 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); in xilinx_dma_stop_transfer()
1284 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, in xilinx_dma_stop_transfer()
1295 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan) in xilinx_cdma_stop_transfer() argument
1299 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, in xilinx_cdma_stop_transfer()
1308 static void xilinx_dma_start(struct xilinx_dma_chan *chan) in xilinx_dma_start() argument
1313 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); in xilinx_dma_start()
1316 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, in xilinx_dma_start()
1321 dev_err(chan->dev, "Cannot start channel %p: %x\n", in xilinx_dma_start()
1322 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); in xilinx_dma_start()
1324 chan->err = true; in xilinx_dma_start()
1332 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) in xilinx_vdma_start_transfer() argument
1334 struct xilinx_vdma_config *config = &chan->config; in xilinx_vdma_start_transfer()
1341 if (chan->err) in xilinx_vdma_start_transfer()
1344 if (!chan->idle) in xilinx_vdma_start_transfer()
1347 if (list_empty(&chan->pending_list)) in xilinx_vdma_start_transfer()
1350 desc = list_first_entry(&chan->pending_list, in xilinx_vdma_start_transfer()
1354 if (chan->has_vflip) { in xilinx_vdma_start_transfer()
1355 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP); in xilinx_vdma_start_transfer()
1358 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP, in xilinx_vdma_start_transfer()
1362 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_vdma_start_transfer()
1375 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); in xilinx_vdma_start_transfer()
1377 j = chan->desc_submitcount; in xilinx_vdma_start_transfer()
1378 reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR); in xilinx_vdma_start_transfer()
1379 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_vdma_start_transfer()
1386 dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg); in xilinx_vdma_start_transfer()
1389 xilinx_dma_start(chan); in xilinx_vdma_start_transfer()
1391 if (chan->err) in xilinx_vdma_start_transfer()
1395 if (chan->desc_submitcount < chan->num_frms) in xilinx_vdma_start_transfer()
1396 i = chan->desc_submitcount; in xilinx_vdma_start_transfer()
1399 if (chan->ext_addr) in xilinx_vdma_start_transfer()
1400 vdma_desc_write_64(chan, in xilinx_vdma_start_transfer()
1405 vdma_desc_write(chan, in xilinx_vdma_start_transfer()
1416 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); in xilinx_vdma_start_transfer()
1417 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, in xilinx_vdma_start_transfer()
1419 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); in xilinx_vdma_start_transfer()
1421 chan->desc_submitcount++; in xilinx_vdma_start_transfer()
1422 chan->desc_pendingcount--; in xilinx_vdma_start_transfer()
1424 list_add_tail(&desc->node, &chan->active_list); in xilinx_vdma_start_transfer()
1425 if (chan->desc_submitcount == chan->num_frms) in xilinx_vdma_start_transfer()
1426 chan->desc_submitcount = 0; in xilinx_vdma_start_transfer()
1428 chan->idle = false; in xilinx_vdma_start_transfer()
1435 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan) in xilinx_cdma_start_transfer() argument
1439 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR); in xilinx_cdma_start_transfer()
1441 if (chan->err) in xilinx_cdma_start_transfer()
1444 if (!chan->idle) in xilinx_cdma_start_transfer()
1447 if (list_empty(&chan->pending_list)) in xilinx_cdma_start_transfer()
1450 head_desc = list_first_entry(&chan->pending_list, in xilinx_cdma_start_transfer()
1452 tail_desc = list_last_entry(&chan->pending_list, in xilinx_cdma_start_transfer()
1457 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { in xilinx_cdma_start_transfer()
1459 ctrl_reg |= chan->desc_pendingcount << in xilinx_cdma_start_transfer()
1461 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg); in xilinx_cdma_start_transfer()
1464 if (chan->has_sg) { in xilinx_cdma_start_transfer()
1465 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, in xilinx_cdma_start_transfer()
1468 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, in xilinx_cdma_start_transfer()
1471 xilinx_write(chan, XILINX_DMA_REG_CURDESC, in xilinx_cdma_start_transfer()
1475 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, in xilinx_cdma_start_transfer()
1488 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, in xilinx_cdma_start_transfer()
1490 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, in xilinx_cdma_start_transfer()
1494 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, in xilinx_cdma_start_transfer()
1495 hw->control & chan->xdev->max_buffer_len); in xilinx_cdma_start_transfer()
1498 list_splice_tail_init(&chan->pending_list, &chan->active_list); in xilinx_cdma_start_transfer()
1499 chan->desc_pendingcount = 0; in xilinx_cdma_start_transfer()
1500 chan->idle = false; in xilinx_cdma_start_transfer()
1507 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) in xilinx_dma_start_transfer() argument
1513 if (chan->err) in xilinx_dma_start_transfer()
1516 if (list_empty(&chan->pending_list)) in xilinx_dma_start_transfer()
1519 if (!chan->idle) in xilinx_dma_start_transfer()
1522 head_desc = list_first_entry(&chan->pending_list, in xilinx_dma_start_transfer()
1524 tail_desc = list_last_entry(&chan->pending_list, in xilinx_dma_start_transfer()
1529 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_dma_start_transfer()
1531 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { in xilinx_dma_start_transfer()
1533 reg |= chan->desc_pendingcount << in xilinx_dma_start_transfer()
1535 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); in xilinx_dma_start_transfer()
1538 if (chan->has_sg) in xilinx_dma_start_transfer()
1539 xilinx_write(chan, XILINX_DMA_REG_CURDESC, in xilinx_dma_start_transfer()
1542 xilinx_dma_start(chan); in xilinx_dma_start_transfer()
1544 if (chan->err) in xilinx_dma_start_transfer()
1548 if (chan->has_sg) { in xilinx_dma_start_transfer()
1549 if (chan->cyclic) in xilinx_dma_start_transfer()
1550 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, in xilinx_dma_start_transfer()
1551 chan->cyclic_seg_v->phys); in xilinx_dma_start_transfer()
1553 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, in xilinx_dma_start_transfer()
1564 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, in xilinx_dma_start_transfer()
1568 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, in xilinx_dma_start_transfer()
1569 hw->control & chan->xdev->max_buffer_len); in xilinx_dma_start_transfer()
1572 list_splice_tail_init(&chan->pending_list, &chan->active_list); in xilinx_dma_start_transfer()
1573 chan->desc_pendingcount = 0; in xilinx_dma_start_transfer()
1574 chan->idle = false; in xilinx_dma_start_transfer()
1581 static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan) in xilinx_mcdma_start_transfer() argument
1592 if (chan->err) in xilinx_mcdma_start_transfer()
1595 if (!chan->idle) in xilinx_mcdma_start_transfer()
1598 if (list_empty(&chan->pending_list)) in xilinx_mcdma_start_transfer()
1601 head_desc = list_first_entry(&chan->pending_list, in xilinx_mcdma_start_transfer()
1603 tail_desc = list_last_entry(&chan->pending_list, in xilinx_mcdma_start_transfer()
1608 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); in xilinx_mcdma_start_transfer()
1610 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) { in xilinx_mcdma_start_transfer()
1612 reg |= chan->desc_pendingcount << in xilinx_mcdma_start_transfer()
1617 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); in xilinx_mcdma_start_transfer()
1620 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), in xilinx_mcdma_start_transfer()
1624 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET); in xilinx_mcdma_start_transfer()
1625 reg |= BIT(chan->tdest); in xilinx_mcdma_start_transfer()
1626 dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg); in xilinx_mcdma_start_transfer()
1629 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); in xilinx_mcdma_start_transfer()
1631 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); in xilinx_mcdma_start_transfer()
1633 xilinx_dma_start(chan); in xilinx_mcdma_start_transfer()
1635 if (chan->err) in xilinx_mcdma_start_transfer()
1639 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest), in xilinx_mcdma_start_transfer()
1642 list_splice_tail_init(&chan->pending_list, &chan->active_list); in xilinx_mcdma_start_transfer()
1643 chan->desc_pendingcount = 0; in xilinx_mcdma_start_transfer()
1644 chan->idle = false; in xilinx_mcdma_start_transfer()
1653 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_issue_pending() local
1656 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_issue_pending()
1657 chan->start_transfer(chan); in xilinx_dma_issue_pending()
1658 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_issue_pending()
1667 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) in xilinx_dma_complete_descriptor() argument
1672 if (list_empty(&chan->active_list)) in xilinx_dma_complete_descriptor()
1675 list_for_each_entry_safe(desc, next, &chan->active_list, node) { in xilinx_dma_complete_descriptor()
1676 if (chan->has_sg && chan->xdev->dma_config->dmatype != in xilinx_dma_complete_descriptor()
1678 desc->residue = xilinx_dma_get_residue(chan, desc); in xilinx_dma_complete_descriptor()
1681 desc->err = chan->err; in xilinx_dma_complete_descriptor()
1686 list_add_tail(&desc->node, &chan->done_list); in xilinx_dma_complete_descriptor()
1696 static int xilinx_dma_reset(struct xilinx_dma_chan *chan) in xilinx_dma_reset() argument
1701 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET); in xilinx_dma_reset()
1704 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, in xilinx_dma_reset()
1709 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", in xilinx_dma_reset()
1710 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR), in xilinx_dma_reset()
1711 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); in xilinx_dma_reset()
1715 chan->err = false; in xilinx_dma_reset()
1716 chan->idle = true; in xilinx_dma_reset()
1717 chan->desc_pendingcount = 0; in xilinx_dma_reset()
1718 chan->desc_submitcount = 0; in xilinx_dma_reset()
1729 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan) in xilinx_dma_chan_reset() argument
1734 err = xilinx_dma_reset(chan); in xilinx_dma_chan_reset()
1739 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, in xilinx_dma_chan_reset()
1754 struct xilinx_dma_chan *chan = data; in xilinx_mcdma_irq_handler() local
1757 if (chan->direction == DMA_DEV_TO_MEM) in xilinx_mcdma_irq_handler()
1763 chan_sermask = dma_ctrl_read(chan, ser_offset); in xilinx_mcdma_irq_handler()
1769 if (chan->direction == DMA_DEV_TO_MEM) in xilinx_mcdma_irq_handler()
1770 chan_offset = chan->xdev->dma_config->max_channels / 2; in xilinx_mcdma_irq_handler()
1773 chan = chan->xdev->chan[chan_offset]; in xilinx_mcdma_irq_handler()
1775 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest)); in xilinx_mcdma_irq_handler()
1779 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest), in xilinx_mcdma_irq_handler()
1783 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n", in xilinx_mcdma_irq_handler()
1784 chan, in xilinx_mcdma_irq_handler()
1785 dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET), in xilinx_mcdma_irq_handler()
1786 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET in xilinx_mcdma_irq_handler()
1787 (chan->tdest)), in xilinx_mcdma_irq_handler()
1788 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET in xilinx_mcdma_irq_handler()
1789 (chan->tdest))); in xilinx_mcdma_irq_handler()
1790 chan->err = true; in xilinx_mcdma_irq_handler()
1798 dev_dbg(chan->dev, "Inter-packet latency too long\n"); in xilinx_mcdma_irq_handler()
1802 spin_lock(&chan->lock); in xilinx_mcdma_irq_handler()
1803 xilinx_dma_complete_descriptor(chan); in xilinx_mcdma_irq_handler()
1804 chan->idle = true; in xilinx_mcdma_irq_handler()
1805 chan->start_transfer(chan); in xilinx_mcdma_irq_handler()
1806 spin_unlock(&chan->lock); in xilinx_mcdma_irq_handler()
1809 tasklet_schedule(&chan->tasklet); in xilinx_mcdma_irq_handler()
1822 struct xilinx_dma_chan *chan = data; in xilinx_dma_irq_handler() local
1826 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); in xilinx_dma_irq_handler()
1830 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, in xilinx_dma_irq_handler()
1843 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, in xilinx_dma_irq_handler()
1846 if (!chan->flush_on_fsync || in xilinx_dma_irq_handler()
1848 dev_err(chan->dev, in xilinx_dma_irq_handler()
1850 chan, errors, in xilinx_dma_irq_handler()
1851 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC), in xilinx_dma_irq_handler()
1852 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC)); in xilinx_dma_irq_handler()
1853 chan->err = true; in xilinx_dma_irq_handler()
1862 dev_dbg(chan->dev, "Inter-packet latency too long\n"); in xilinx_dma_irq_handler()
1866 spin_lock(&chan->lock); in xilinx_dma_irq_handler()
1867 xilinx_dma_complete_descriptor(chan); in xilinx_dma_irq_handler()
1868 chan->idle = true; in xilinx_dma_irq_handler()
1869 chan->start_transfer(chan); in xilinx_dma_irq_handler()
1870 spin_unlock(&chan->lock); in xilinx_dma_irq_handler()
1873 tasklet_schedule(&chan->tasklet); in xilinx_dma_irq_handler()
1882 static void append_desc_queue(struct xilinx_dma_chan *chan, in append_desc_queue() argument
1891 if (list_empty(&chan->pending_list)) in append_desc_queue()
1898 tail_desc = list_last_entry(&chan->pending_list, in append_desc_queue()
1900 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in append_desc_queue()
1905 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in append_desc_queue()
1910 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in append_desc_queue()
1928 list_add_tail(&desc->node, &chan->pending_list); in append_desc_queue()
1929 chan->desc_pendingcount++; in append_desc_queue()
1931 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) in append_desc_queue()
1932 && unlikely(chan->desc_pendingcount > chan->num_frms)) { in append_desc_queue()
1933 dev_dbg(chan->dev, "desc pendingcount is too high\n"); in append_desc_queue()
1934 chan->desc_pendingcount = chan->num_frms; in append_desc_queue()
1947 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); in xilinx_dma_tx_submit() local
1952 if (chan->cyclic) { in xilinx_dma_tx_submit()
1953 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_dma_tx_submit()
1957 if (chan->err) { in xilinx_dma_tx_submit()
1962 err = xilinx_dma_chan_reset(chan); in xilinx_dma_tx_submit()
1967 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_tx_submit()
1972 append_desc_queue(chan, desc); in xilinx_dma_tx_submit()
1975 chan->cyclic = true; in xilinx_dma_tx_submit()
1977 chan->terminating = false; in xilinx_dma_tx_submit()
1979 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_tx_submit()
1998 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_vdma_dma_prep_interleaved() local
2013 desc = xilinx_dma_alloc_tx_descriptor(chan); in xilinx_vdma_dma_prep_interleaved()
2017 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_vdma_dma_prep_interleaved()
2022 segment = xilinx_vdma_alloc_tx_segment(chan); in xilinx_vdma_dma_prep_interleaved()
2032 hw->stride |= chan->config.frm_dly << in xilinx_vdma_dma_prep_interleaved()
2036 if (chan->ext_addr) { in xilinx_vdma_dma_prep_interleaved()
2043 if (chan->ext_addr) { in xilinx_vdma_dma_prep_interleaved()
2062 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_vdma_dma_prep_interleaved()
2080 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_cdma_prep_memcpy() local
2085 if (!len || len > chan->xdev->max_buffer_len) in xilinx_cdma_prep_memcpy()
2088 desc = xilinx_dma_alloc_tx_descriptor(chan); in xilinx_cdma_prep_memcpy()
2092 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_cdma_prep_memcpy()
2096 segment = xilinx_cdma_alloc_tx_segment(chan); in xilinx_cdma_prep_memcpy()
2104 if (chan->ext_addr) { in xilinx_cdma_prep_memcpy()
2118 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_cdma_prep_memcpy()
2138 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_prep_slave_sg() local
2151 desc = xilinx_dma_alloc_tx_descriptor(chan); in xilinx_dma_prep_slave_sg()
2155 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_dma_prep_slave_sg()
2167 segment = xilinx_axidma_alloc_tx_segment(chan); in xilinx_dma_prep_slave_sg()
2175 copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), in xilinx_dma_prep_slave_sg()
2180 xilinx_axidma_buf(chan, hw, sg_dma_address(sg), in xilinx_dma_prep_slave_sg()
2185 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_dma_prep_slave_sg()
2206 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_dma_prep_slave_sg()
2217 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_dma_prep_slave_sg()
2237 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_prep_dma_cyclic() local
2257 desc = xilinx_dma_alloc_tx_descriptor(chan); in xilinx_dma_prep_dma_cyclic()
2261 chan->direction = direction; in xilinx_dma_prep_dma_cyclic()
2262 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_dma_prep_dma_cyclic()
2272 segment = xilinx_axidma_alloc_tx_segment(chan); in xilinx_dma_prep_dma_cyclic()
2280 copy = xilinx_dma_calc_copysize(chan, period_len, in xilinx_dma_prep_dma_cyclic()
2283 xilinx_axidma_buf(chan, hw, buf_addr, sg_used, in xilinx_dma_prep_dma_cyclic()
2306 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_dma_prep_dma_cyclic()
2308 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); in xilinx_dma_prep_dma_cyclic()
2324 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_dma_prep_dma_cyclic()
2345 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_mcdma_prep_slave_sg() local
2358 desc = xilinx_dma_alloc_tx_descriptor(chan); in xilinx_mcdma_prep_slave_sg()
2362 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_mcdma_prep_slave_sg()
2374 segment = xilinx_aximcdma_alloc_tx_segment(chan); in xilinx_mcdma_prep_slave_sg()
2383 chan->xdev->max_buffer_len); in xilinx_mcdma_prep_slave_sg()
2387 xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg), in xilinx_mcdma_prep_slave_sg()
2391 if (chan->direction == DMA_MEM_TO_DEV && app_w) { in xilinx_mcdma_prep_slave_sg()
2410 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_mcdma_prep_slave_sg()
2421 xilinx_dma_free_tx_descriptor(chan, desc); in xilinx_mcdma_prep_slave_sg()
2434 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_dma_terminate_all() local
2438 if (!chan->cyclic) { in xilinx_dma_terminate_all()
2439 err = chan->stop_transfer(chan); in xilinx_dma_terminate_all()
2441 dev_err(chan->dev, "Cannot stop channel %p: %x\n", in xilinx_dma_terminate_all()
2442 chan, dma_ctrl_read(chan, in xilinx_dma_terminate_all()
2444 chan->err = true; in xilinx_dma_terminate_all()
2448 xilinx_dma_chan_reset(chan); in xilinx_dma_terminate_all()
2450 chan->terminating = true; in xilinx_dma_terminate_all()
2451 xilinx_dma_free_descriptors(chan); in xilinx_dma_terminate_all()
2452 chan->idle = true; in xilinx_dma_terminate_all()
2454 if (chan->cyclic) { in xilinx_dma_terminate_all()
2455 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_dma_terminate_all()
2457 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); in xilinx_dma_terminate_all()
2458 chan->cyclic = false; in xilinx_dma_terminate_all()
2461 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) in xilinx_dma_terminate_all()
2462 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, in xilinx_dma_terminate_all()
2484 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); in xilinx_vdma_channel_set_config() local
2488 return xilinx_dma_chan_reset(chan); in xilinx_vdma_channel_set_config()
2490 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_vdma_channel_set_config()
2492 chan->config.frm_dly = cfg->frm_dly; in xilinx_vdma_channel_set_config()
2493 chan->config.park = cfg->park; in xilinx_vdma_channel_set_config()
2496 chan->config.gen_lock = cfg->gen_lock; in xilinx_vdma_channel_set_config()
2497 chan->config.master = cfg->master; in xilinx_vdma_channel_set_config()
2500 if (cfg->gen_lock && chan->genlock) { in xilinx_vdma_channel_set_config()
2506 chan->config.frm_cnt_en = cfg->frm_cnt_en; in xilinx_vdma_channel_set_config()
2507 chan->config.vflip_en = cfg->vflip_en; in xilinx_vdma_channel_set_config()
2510 chan->config.park_frm = cfg->park_frm; in xilinx_vdma_channel_set_config()
2512 chan->config.park_frm = -1; in xilinx_vdma_channel_set_config()
2514 chan->config.coalesc = cfg->coalesc; in xilinx_vdma_channel_set_config()
2515 chan->config.delay = cfg->delay; in xilinx_vdma_channel_set_config()
2520 chan->config.coalesc = cfg->coalesc; in xilinx_vdma_channel_set_config()
2526 chan->config.delay = cfg->delay; in xilinx_vdma_channel_set_config()
2533 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr); in xilinx_vdma_channel_set_config()
2547 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan) in xilinx_dma_chan_remove() argument
2550 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, in xilinx_dma_chan_remove()
2553 if (chan->irq > 0) in xilinx_dma_chan_remove()
2554 free_irq(chan->irq, chan); in xilinx_dma_chan_remove()
2556 tasklet_kill(&chan->tasklet); in xilinx_dma_chan_remove()
2558 list_del(&chan->common.device_node); in xilinx_dma_chan_remove()
2752 struct xilinx_dma_chan *chan; in xilinx_dma_chan_probe() local
2758 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); in xilinx_dma_chan_probe()
2759 if (!chan) in xilinx_dma_chan_probe()
2762 chan->dev = xdev->dev; in xilinx_dma_chan_probe()
2763 chan->xdev = xdev; in xilinx_dma_chan_probe()
2764 chan->desc_pendingcount = 0x0; in xilinx_dma_chan_probe()
2765 chan->ext_addr = xdev->ext_addr; in xilinx_dma_chan_probe()
2771 chan->idle = true; in xilinx_dma_chan_probe()
2773 spin_lock_init(&chan->lock); in xilinx_dma_chan_probe()
2774 INIT_LIST_HEAD(&chan->pending_list); in xilinx_dma_chan_probe()
2775 INIT_LIST_HEAD(&chan->done_list); in xilinx_dma_chan_probe()
2776 INIT_LIST_HEAD(&chan->active_list); in xilinx_dma_chan_probe()
2777 INIT_LIST_HEAD(&chan->free_seg_list); in xilinx_dma_chan_probe()
2782 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); in xilinx_dma_chan_probe()
2801 chan->direction = DMA_MEM_TO_DEV; in xilinx_dma_chan_probe()
2802 chan->id = xdev->mm2s_chan_id++; in xilinx_dma_chan_probe()
2803 chan->tdest = chan->id; in xilinx_dma_chan_probe()
2805 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; in xilinx_dma_chan_probe()
2807 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; in xilinx_dma_chan_probe()
2808 chan->config.park = 1; in xilinx_dma_chan_probe()
2812 chan->flush_on_fsync = true; in xilinx_dma_chan_probe()
2818 chan->direction = DMA_DEV_TO_MEM; in xilinx_dma_chan_probe()
2819 chan->id = xdev->s2mm_chan_id++; in xilinx_dma_chan_probe()
2820 chan->tdest = chan->id - xdev->dma_config->max_channels / 2; in xilinx_dma_chan_probe()
2821 chan->has_vflip = of_property_read_bool(node, in xilinx_dma_chan_probe()
2823 if (chan->has_vflip) { in xilinx_dma_chan_probe()
2824 chan->config.vflip_en = dma_read(chan, in xilinx_dma_chan_probe()
2830 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; in xilinx_dma_chan_probe()
2832 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; in xilinx_dma_chan_probe()
2835 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; in xilinx_dma_chan_probe()
2836 chan->config.park = 1; in xilinx_dma_chan_probe()
2840 chan->flush_on_fsync = true; in xilinx_dma_chan_probe()
2848 chan->irq = irq_of_parse_and_map(node, chan->tdest); in xilinx_dma_chan_probe()
2849 err = request_irq(chan->irq, xdev->dma_config->irq_handler, in xilinx_dma_chan_probe()
2850 IRQF_SHARED, "xilinx-dma-controller", chan); in xilinx_dma_chan_probe()
2852 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq); in xilinx_dma_chan_probe()
2857 chan->start_transfer = xilinx_dma_start_transfer; in xilinx_dma_chan_probe()
2858 chan->stop_transfer = xilinx_dma_stop_transfer; in xilinx_dma_chan_probe()
2860 chan->start_transfer = xilinx_mcdma_start_transfer; in xilinx_dma_chan_probe()
2861 chan->stop_transfer = xilinx_dma_stop_transfer; in xilinx_dma_chan_probe()
2863 chan->start_transfer = xilinx_cdma_start_transfer; in xilinx_dma_chan_probe()
2864 chan->stop_transfer = xilinx_cdma_stop_transfer; in xilinx_dma_chan_probe()
2866 chan->start_transfer = xilinx_vdma_start_transfer; in xilinx_dma_chan_probe()
2867 chan->stop_transfer = xilinx_dma_stop_transfer; in xilinx_dma_chan_probe()
2873 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & in xilinx_dma_chan_probe()
2875 chan->has_sg = true; in xilinx_dma_chan_probe()
2876 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id, in xilinx_dma_chan_probe()
2877 chan->has_sg ? "enabled" : "disabled"); in xilinx_dma_chan_probe()
2881 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet); in xilinx_dma_chan_probe()
2887 chan->common.device = &xdev->common; in xilinx_dma_chan_probe()
2889 list_add_tail(&chan->common.device_node, &xdev->common.channels); in xilinx_dma_chan_probe()
2890 xdev->chan[chan->id] = chan; in xilinx_dma_chan_probe()
2893 err = xilinx_dma_chan_reset(chan); in xilinx_dma_chan_probe()
2941 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id]) in of_dma_xilinx_xlate()
2944 return dma_get_slave_channel(&xdev->chan[chan_id]->common); in of_dma_xilinx_xlate()
3128 if (xdev->chan[i]) in xilinx_dma_probe()
3129 xdev->chan[i]->num_frms = num_frames; in xilinx_dma_probe()
3160 if (xdev->chan[i]) in xilinx_dma_probe()
3161 xilinx_dma_chan_remove(xdev->chan[i]); in xilinx_dma_probe()
3184 if (xdev->chan[i]) in xilinx_dma_remove()
3185 xilinx_dma_chan_remove(xdev->chan[i]); in xilinx_dma_remove()