Lines Matching +full:0 +full:xf04
10 #define PCILYNX_MAX_REGISTER 0xfff
11 #define PCILYNX_MAX_MEMORY 0xffff
13 #define PCI_LATENCY_CACHELINE 0x0c
15 #define MISC_CONTROL 0x40
16 #define MISC_CONTROL_SWRESET (1<<0)
18 #define SERIAL_EEPROM_CONTROL 0x44
20 #define PCI_INT_STATUS 0x48
21 #define PCI_INT_ENABLE 0x4c
42 #define PCI_INT_DMA0_HLT (1<<0)
44 #define PCI_INT_DMA_ALL 0x3ff
49 #define LBUS_ADDR 0xb4
50 #define LBUS_ADDR_SEL_RAM (0x0<<16)
51 #define LBUS_ADDR_SEL_ROM (0x1<<16)
52 #define LBUS_ADDR_SEL_AUX (0x2<<16)
53 #define LBUS_ADDR_SEL_ZV (0x3<<16)
55 #define GPIO_CTRL_A 0xb8
56 #define GPIO_CTRL_B 0xbc
57 #define GPIO_DATA_BASE 0xc0
59 #define DMA_BREG(base, chan) (base + chan * 0x20)
60 #define DMA_SREG(base, chan) (base + chan * 0x10)
62 #define PCL_NEXT_INVALID (1<<0)
65 #define PCL_CMD_RCV (0x1<<24)
66 #define PCL_CMD_RCV_AND_UPDATE (0xa<<24)
67 #define PCL_CMD_XMT (0x2<<24)
68 #define PCL_CMD_UNFXMT (0xc<<24)
69 #define PCL_CMD_PCI_TO_LBUS (0x8<<24)
70 #define PCL_CMD_LBUS_TO_PCI (0x9<<24)
73 #define PCL_CMD_NOP (0x0<<24)
74 #define PCL_CMD_LOAD (0x3<<24)
75 #define PCL_CMD_STOREQ (0x4<<24)
76 #define PCL_CMD_STORED (0xb<<24)
77 #define PCL_CMD_STORE0 (0x5<<24)
78 #define PCL_CMD_STORE1 (0x6<<24)
79 #define PCL_CMD_COMPARE (0xe<<24)
80 #define PCL_CMD_SWAP_COMPARE (0xf<<24)
81 #define PCL_CMD_ADD (0xd<<24)
82 #define PCL_CMD_BRANCH (0x7<<24)
85 #define PCL_COND_DMARDY_SET (0x1<<20)
86 #define PCL_COND_DMARDY_CLEAR (0x2<<20)
95 #define DMA0_PREV_PCL 0x100
96 #define DMA1_PREV_PCL 0x120
97 #define DMA2_PREV_PCL 0x140
98 #define DMA3_PREV_PCL 0x160
99 #define DMA4_PREV_PCL 0x180
102 #define DMA0_CURRENT_PCL 0x104
103 #define DMA1_CURRENT_PCL 0x124
104 #define DMA2_CURRENT_PCL 0x144
105 #define DMA3_CURRENT_PCL 0x164
106 #define DMA4_CURRENT_PCL 0x184
109 #define DMA0_CHAN_STAT 0x10c
110 #define DMA1_CHAN_STAT 0x12c
111 #define DMA2_CHAN_STAT 0x14c
112 #define DMA3_CHAN_STAT 0x16c
113 #define DMA4_CHAN_STAT 0x18c
123 #define DMA0_CHAN_CTRL 0x110
124 #define DMA1_CHAN_CTRL 0x130
125 #define DMA2_CHAN_CTRL 0x150
126 #define DMA3_CHAN_CTRL 0x170
127 #define DMA4_CHAN_CTRL 0x190
134 #define DMA0_READY 0x114
135 #define DMA1_READY 0x134
136 #define DMA2_READY 0x154
137 #define DMA3_READY 0x174
138 #define DMA4_READY 0x194
141 #define DMA_GLOBAL_REGISTER 0x908
143 #define FIFO_SIZES 0xa00
145 #define FIFO_CONTROL 0xa10
150 #define FIFO_XMIT_THRESHOLD 0xa14
152 #define DMA0_WORD0_CMP_VALUE 0xb00
153 #define DMA1_WORD0_CMP_VALUE 0xb10
154 #define DMA2_WORD0_CMP_VALUE 0xb20
155 #define DMA3_WORD0_CMP_VALUE 0xb30
156 #define DMA4_WORD0_CMP_VALUE 0xb40
159 #define DMA0_WORD0_CMP_ENABLE 0xb04
160 #define DMA1_WORD0_CMP_ENABLE 0xb14
161 #define DMA2_WORD0_CMP_ENABLE 0xb24
162 #define DMA3_WORD0_CMP_ENABLE 0xb34
163 #define DMA4_WORD0_CMP_ENABLE 0xb44
166 #define DMA0_WORD1_CMP_VALUE 0xb08
167 #define DMA1_WORD1_CMP_VALUE 0xb18
168 #define DMA2_WORD1_CMP_VALUE 0xb28
169 #define DMA3_WORD1_CMP_VALUE 0xb38
170 #define DMA4_WORD1_CMP_VALUE 0xb48
173 #define DMA0_WORD1_CMP_ENABLE 0xb0c
174 #define DMA1_WORD1_CMP_ENABLE 0xb1c
175 #define DMA2_WORD1_CMP_ENABLE 0xb2c
176 #define DMA3_WORD1_CMP_ENABLE 0xb3c
177 #define DMA4_WORD1_CMP_ENABLE 0xb4c
188 #define LINK_ID 0xf00
192 #define LINK_CONTROL 0xf04
206 #define CYCLE_TIMER 0xf08
208 #define LINK_PHY 0xf0c
215 #define LINK_INT_STATUS 0xf14
216 #define LINK_INT_ENABLE 0xf18
238 #define LINK_INT_IARB_FAILED (1<<0)