100 				     const struct aspeed_sgpio_bank *bank,  in bank_reg()  argument
105 		return gpio->base + bank->val_regs + GPIO_VAL_VALUE;  in bank_reg()
107 		return gpio->base + bank->rdata_reg;  in bank_reg()
109 		return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;  in bank_reg()
111 		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;  in bank_reg()
113 		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;  in bank_reg()
115 		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;  in bank_reg()
117 		return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;  in bank_reg()
130 	unsigned int bank;  in to_bank()  local
132 	bank = GPIO_BANK(offset);  in to_bank()
134 	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));  in to_bank()
135 	return &aspeed_sgpio_banks[bank];  in to_bank()
179 	const struct aspeed_sgpio_bank *bank = to_bank(offset);  in aspeed_sgpio_get()  local
187 	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));  in aspeed_sgpio_get()
197 	const struct aspeed_sgpio_bank *bank = to_bank(offset);  in sgpio_set_value()  local
206 	addr_r = bank_reg(gpio, bank, reg_rdata);  in sgpio_set_value()
207 	addr_w = bank_reg(gpio, bank, reg_val);  in sgpio_set_value()
261 					const struct aspeed_sgpio_bank **bank,  in irqd_to_aspeed_sgpio_data()  argument
271 	*bank = to_bank(*offset);  in irqd_to_aspeed_sgpio_data()
277 	const struct aspeed_sgpio_bank *bank;  in aspeed_sgpio_irq_ack()  local
284 	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);  in aspeed_sgpio_irq_ack()
286 	status_addr = bank_reg(gpio, bank, reg_irq_status);  in aspeed_sgpio_irq_ack()
297 	const struct aspeed_sgpio_bank *bank;  in aspeed_sgpio_irq_set_mask()  local
304 	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);  in aspeed_sgpio_irq_set_mask()
305 	addr = bank_reg(gpio, bank, reg_irq_enable);  in aspeed_sgpio_irq_set_mask()
336 	const struct aspeed_sgpio_bank *bank;  in aspeed_sgpio_set_type()  local
343 	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);  in aspeed_sgpio_set_type()
368 	addr = bank_reg(gpio, bank, reg_irq_type0);  in aspeed_sgpio_set_type()
373 	addr = bank_reg(gpio, bank, reg_irq_type1);  in aspeed_sgpio_set_type()
378 	addr = bank_reg(gpio, bank, reg_irq_type2);  in aspeed_sgpio_set_type()
401 		const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];  in aspeed_sgpio_irq_handler()  local
403 		reg = ioread32(bank_reg(data, bank, reg_irq_status));  in aspeed_sgpio_irq_handler()
427 	const struct aspeed_sgpio_bank *bank;  in aspeed_sgpio_setup_irqs()  local
438 		bank =  &aspeed_sgpio_banks[i];  in aspeed_sgpio_setup_irqs()
440 		iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));  in aspeed_sgpio_setup_irqs()
442 		iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));  in aspeed_sgpio_setup_irqs()
457 		bank = &aspeed_sgpio_banks[i];  in aspeed_sgpio_setup_irqs()
459 		iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));  in aspeed_sgpio_setup_irqs()
461 		iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));  in aspeed_sgpio_setup_irqs()
463 		iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2));  in aspeed_sgpio_setup_irqs()