Lines Matching +full:cpu +full:- +full:offset
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
22 * - the basic variant, called "orion-gpio", with the simplest
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
29 * - the armadaxp variant for Armada XP systems. This variant keeps
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
75 /* The MV78200 has per-CPU registers for edge mask and level mask */
76 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) argument
77 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) argument
80 * The Armada XP has per-CPU registers for interrupt cause, interrupt
84 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) argument
85 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) argument
86 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) argument
112 u32 offset; member
137 struct regmap **map, unsigned int *offset) in mvebu_gpioreg_edge_cause() argument
139 int cpu; in mvebu_gpioreg_edge_cause() local
141 switch (mvchip->soc_variant) { in mvebu_gpioreg_edge_cause()
145 *map = mvchip->regs; in mvebu_gpioreg_edge_cause()
146 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; in mvebu_gpioreg_edge_cause()
149 cpu = smp_processor_id(); in mvebu_gpioreg_edge_cause()
150 *map = mvchip->percpu_regs; in mvebu_gpioreg_edge_cause()
151 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); in mvebu_gpioreg_edge_cause()
162 unsigned int offset; in mvebu_gpio_read_edge_cause() local
165 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); in mvebu_gpio_read_edge_cause()
166 regmap_read(map, offset, &val); in mvebu_gpio_read_edge_cause()
175 unsigned int offset; in mvebu_gpio_write_edge_cause() local
177 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); in mvebu_gpio_write_edge_cause()
178 regmap_write(map, offset, val); in mvebu_gpio_write_edge_cause()
183 struct regmap **map, unsigned int *offset) in mvebu_gpioreg_edge_mask() argument
185 int cpu; in mvebu_gpioreg_edge_mask() local
187 switch (mvchip->soc_variant) { in mvebu_gpioreg_edge_mask()
190 *map = mvchip->regs; in mvebu_gpioreg_edge_mask()
191 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; in mvebu_gpioreg_edge_mask()
194 cpu = smp_processor_id(); in mvebu_gpioreg_edge_mask()
195 *map = mvchip->regs; in mvebu_gpioreg_edge_mask()
196 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); in mvebu_gpioreg_edge_mask()
199 cpu = smp_processor_id(); in mvebu_gpioreg_edge_mask()
200 *map = mvchip->percpu_regs; in mvebu_gpioreg_edge_mask()
201 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); in mvebu_gpioreg_edge_mask()
212 unsigned int offset; in mvebu_gpio_read_edge_mask() local
215 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); in mvebu_gpio_read_edge_mask()
216 regmap_read(map, offset, &val); in mvebu_gpio_read_edge_mask()
225 unsigned int offset; in mvebu_gpio_write_edge_mask() local
227 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); in mvebu_gpio_write_edge_mask()
228 regmap_write(map, offset, val); in mvebu_gpio_write_edge_mask()
233 struct regmap **map, unsigned int *offset) in mvebu_gpioreg_level_mask() argument
235 int cpu; in mvebu_gpioreg_level_mask() local
237 switch (mvchip->soc_variant) { in mvebu_gpioreg_level_mask()
240 *map = mvchip->regs; in mvebu_gpioreg_level_mask()
241 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; in mvebu_gpioreg_level_mask()
244 cpu = smp_processor_id(); in mvebu_gpioreg_level_mask()
245 *map = mvchip->regs; in mvebu_gpioreg_level_mask()
246 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); in mvebu_gpioreg_level_mask()
249 cpu = smp_processor_id(); in mvebu_gpioreg_level_mask()
250 *map = mvchip->percpu_regs; in mvebu_gpioreg_level_mask()
251 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); in mvebu_gpioreg_level_mask()
262 unsigned int offset; in mvebu_gpio_read_level_mask() local
265 mvebu_gpioreg_level_mask(mvchip, &map, &offset); in mvebu_gpio_read_level_mask()
266 regmap_read(map, offset, &val); in mvebu_gpio_read_level_mask()
275 unsigned int offset; in mvebu_gpio_write_level_mask() local
277 mvebu_gpioreg_level_mask(mvchip, &map, &offset); in mvebu_gpio_write_level_mask()
278 regmap_write(map, offset, val); in mvebu_gpio_write_level_mask()
287 return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF; in mvebu_pwmreg_blink_on_duration()
292 return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF; in mvebu_pwmreg_blink_off_duration()
302 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_set()
311 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_get()
316 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, in mvebu_gpio_get()
318 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_get()
322 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); in mvebu_gpio_get()
333 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_blink()
346 ret = pinctrl_gpio_direction_input(chip->base + pin); in mvebu_gpio_direction_input()
350 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_direction_input()
366 ret = pinctrl_gpio_direction_output(chip->base + pin); in mvebu_gpio_direction_output()
373 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_direction_output()
384 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_get_direction()
396 return irq_create_mapping(mvchip->domain, pin); in mvebu_gpio_to_irq()
405 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_irq_ack()
406 u32 mask = d->mask; in mvebu_gpio_irq_ack()
416 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_edge_irq_mask()
418 u32 mask = d->mask; in mvebu_gpio_edge_irq_mask()
421 ct->mask_cache_priv &= ~mask; in mvebu_gpio_edge_irq_mask()
422 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_edge_irq_mask()
429 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_edge_irq_unmask()
431 u32 mask = d->mask; in mvebu_gpio_edge_irq_unmask()
435 ct->mask_cache_priv |= mask; in mvebu_gpio_edge_irq_unmask()
436 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_edge_irq_unmask()
443 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_level_irq_mask()
445 u32 mask = d->mask; in mvebu_gpio_level_irq_mask()
448 ct->mask_cache_priv &= ~mask; in mvebu_gpio_level_irq_mask()
449 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_level_irq_mask()
456 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_level_irq_unmask()
458 u32 mask = d->mask; in mvebu_gpio_level_irq_unmask()
461 ct->mask_cache_priv |= mask; in mvebu_gpio_level_irq_unmask()
462 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_level_irq_unmask()
476 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
485 * data-in /--------| |-----| |----\
486 * -----| |----- ---- to main cause reg
487 * X \----------------| |----/
496 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_irq_set_type()
500 pin = d->hwirq; in mvebu_gpio_irq_set_type()
502 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_irq_set_type()
504 return -EINVAL; in mvebu_gpio_irq_set_type()
508 return -EINVAL; in mvebu_gpio_irq_set_type()
511 if (!(ct->type & type)) in mvebu_gpio_irq_set_type()
513 return -EINVAL; in mvebu_gpio_irq_set_type()
521 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
522 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
527 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
528 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
534 regmap_read(mvchip->regs, in mvebu_gpio_irq_set_type()
535 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); in mvebu_gpio_irq_set_type()
536 regmap_read(mvchip->regs, in mvebu_gpio_irq_set_type()
537 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_irq_set_type()
547 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
548 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
568 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_irq_handler()
575 for (i = 0; i < mvchip->chip.ngpio; i++) { in mvebu_gpio_irq_handler()
578 irq = irq_find_mapping(mvchip->domain, i); in mvebu_gpio_irq_handler()
588 regmap_read(mvchip->regs, in mvebu_gpio_irq_handler()
589 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_handler()
592 regmap_write(mvchip->regs, in mvebu_gpio_irq_handler()
593 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_handler()
614 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_request()
619 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_request()
621 if (mvpwm->gpiod) { in mvebu_pwm_request()
622 ret = -EBUSY; in mvebu_pwm_request()
624 desc = gpiochip_request_own_desc(&mvchip->chip, in mvebu_pwm_request()
625 pwm->hwpwm, "mvebu-pwm", in mvebu_pwm_request()
633 mvpwm->gpiod = desc; in mvebu_pwm_request()
636 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_request()
645 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_free()
646 gpiochip_free_own_desc(mvpwm->gpiod); in mvebu_pwm_free()
647 mvpwm->gpiod = NULL; in mvebu_pwm_free()
648 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_free()
656 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_get_state()
661 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_get_state()
665 do_div(val, mvpwm->clk_rate); in mvebu_pwm_get_state()
667 state->duty_cycle = UINT_MAX; in mvebu_pwm_get_state()
669 state->duty_cycle = val; in mvebu_pwm_get_state()
671 state->duty_cycle = 1; in mvebu_pwm_get_state()
677 do_div(val, mvpwm->clk_rate); in mvebu_pwm_get_state()
679 state->period = UINT_MAX; in mvebu_pwm_get_state()
681 state->period = val; in mvebu_pwm_get_state()
683 state->period = 1; in mvebu_pwm_get_state()
685 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); in mvebu_pwm_get_state()
687 state->enabled = true; in mvebu_pwm_get_state()
689 state->enabled = false; in mvebu_pwm_get_state()
691 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_get_state()
698 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_apply()
703 if (state->polarity != PWM_POLARITY_NORMAL) in mvebu_pwm_apply()
704 return -EINVAL; in mvebu_pwm_apply()
706 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; in mvebu_pwm_apply()
709 return -EINVAL; in mvebu_pwm_apply()
715 val = (unsigned long long) mvpwm->clk_rate * in mvebu_pwm_apply()
716 (state->period - state->duty_cycle); in mvebu_pwm_apply()
719 return -EINVAL; in mvebu_pwm_apply()
725 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_apply()
729 if (state->enabled) in mvebu_pwm_apply()
730 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); in mvebu_pwm_apply()
732 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); in mvebu_pwm_apply()
734 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_apply()
749 struct mvebu_pwm *mvpwm = mvchip->mvpwm; in mvebu_pwm_suspend()
751 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, in mvebu_pwm_suspend()
752 &mvpwm->blink_select); in mvebu_pwm_suspend()
753 mvpwm->blink_on_duration = in mvebu_pwm_suspend()
755 mvpwm->blink_off_duration = in mvebu_pwm_suspend()
761 struct mvebu_pwm *mvpwm = mvchip->mvpwm; in mvebu_pwm_resume()
763 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, in mvebu_pwm_resume()
764 mvpwm->blink_select); in mvebu_pwm_resume()
765 writel_relaxed(mvpwm->blink_on_duration, in mvebu_pwm_resume()
767 writel_relaxed(mvpwm->blink_off_duration, in mvebu_pwm_resume()
775 struct device *dev = &pdev->dev; in mvebu_pwm_probe()
779 if (!of_device_is_compatible(mvchip->chip.of_node, in mvebu_pwm_probe()
780 "marvell,armada-370-gpio")) in mvebu_pwm_probe()
792 if (IS_ERR(mvchip->clk)) in mvebu_pwm_probe()
793 return PTR_ERR(mvchip->clk); in mvebu_pwm_probe()
804 return -EINVAL; in mvebu_pwm_probe()
805 regmap_write(mvchip->regs, in mvebu_pwm_probe()
806 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); in mvebu_pwm_probe()
810 return -ENOMEM; in mvebu_pwm_probe()
811 mvchip->mvpwm = mvpwm; in mvebu_pwm_probe()
812 mvpwm->mvchip = mvchip; in mvebu_pwm_probe()
814 mvpwm->membase = devm_platform_ioremap_resource_byname(pdev, "pwm"); in mvebu_pwm_probe()
815 if (IS_ERR(mvpwm->membase)) in mvebu_pwm_probe()
816 return PTR_ERR(mvpwm->membase); in mvebu_pwm_probe()
818 mvpwm->clk_rate = clk_get_rate(mvchip->clk); in mvebu_pwm_probe()
819 if (!mvpwm->clk_rate) { in mvebu_pwm_probe()
821 return -EINVAL; in mvebu_pwm_probe()
824 mvpwm->chip.dev = dev; in mvebu_pwm_probe()
825 mvpwm->chip.ops = &mvebu_pwm_ops; in mvebu_pwm_probe()
826 mvpwm->chip.npwm = mvchip->chip.ngpio; in mvebu_pwm_probe()
829 * mvpwm->chip.base to a fixed point like mvchip->chip.base. in mvebu_pwm_probe()
833 mvpwm->chip.base = -1; in mvebu_pwm_probe()
835 spin_lock_init(&mvpwm->lock); in mvebu_pwm_probe()
837 return pwmchip_add(&mvpwm->chip); in mvebu_pwm_probe()
850 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); in mvebu_gpio_dbg_show()
851 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); in mvebu_gpio_dbg_show()
852 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); in mvebu_gpio_dbg_show()
853 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); in mvebu_gpio_dbg_show()
854 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_dbg_show()
866 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); in mvebu_gpio_dbg_show()
875 seq_printf(s, " in %s (act %s) - IRQ", in mvebu_gpio_dbg_show()
895 .compatible = "marvell,orion-gpio",
899 .compatible = "marvell,mv78200-gpio",
903 .compatible = "marvell,armadaxp-gpio",
907 .compatible = "marvell,armada-370-gpio",
911 .compatible = "marvell,armada-8k-gpio",
924 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_suspend()
925 &mvchip->out_reg); in mvebu_gpio_suspend()
926 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_suspend()
927 &mvchip->io_conf_reg); in mvebu_gpio_suspend()
928 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_suspend()
929 &mvchip->blink_en_reg); in mvebu_gpio_suspend()
930 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_suspend()
931 &mvchip->in_pol_reg); in mvebu_gpio_suspend()
933 switch (mvchip->soc_variant) { in mvebu_gpio_suspend()
936 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, in mvebu_gpio_suspend()
937 &mvchip->edge_mask_regs[0]); in mvebu_gpio_suspend()
938 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, in mvebu_gpio_suspend()
939 &mvchip->level_mask_regs[0]); in mvebu_gpio_suspend()
943 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
945 &mvchip->edge_mask_regs[i]); in mvebu_gpio_suspend()
946 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
948 &mvchip->level_mask_regs[i]); in mvebu_gpio_suspend()
953 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
955 &mvchip->edge_mask_regs[i]); in mvebu_gpio_suspend()
956 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
958 &mvchip->level_mask_regs[i]); in mvebu_gpio_suspend()
976 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_resume()
977 mvchip->out_reg); in mvebu_gpio_resume()
978 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_resume()
979 mvchip->io_conf_reg); in mvebu_gpio_resume()
980 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_resume()
981 mvchip->blink_en_reg); in mvebu_gpio_resume()
982 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_resume()
983 mvchip->in_pol_reg); in mvebu_gpio_resume()
985 switch (mvchip->soc_variant) { in mvebu_gpio_resume()
988 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, in mvebu_gpio_resume()
989 mvchip->edge_mask_regs[0]); in mvebu_gpio_resume()
990 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, in mvebu_gpio_resume()
991 mvchip->level_mask_regs[0]); in mvebu_gpio_resume()
995 regmap_write(mvchip->regs, in mvebu_gpio_resume()
997 mvchip->edge_mask_regs[i]); in mvebu_gpio_resume()
998 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1000 mvchip->level_mask_regs[i]); in mvebu_gpio_resume()
1005 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1007 mvchip->edge_mask_regs[i]); in mvebu_gpio_resume()
1008 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1010 mvchip->level_mask_regs[i]); in mvebu_gpio_resume()
1039 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, in mvebu_gpio_probe_raw()
1041 if (IS_ERR(mvchip->regs)) in mvebu_gpio_probe_raw()
1042 return PTR_ERR(mvchip->regs); in mvebu_gpio_probe_raw()
1046 * registers, so no offset is needed. in mvebu_gpio_probe_raw()
1048 mvchip->offset = 0; in mvebu_gpio_probe_raw()
1052 * per-CPU registers in mvebu_gpio_probe_raw()
1054 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { in mvebu_gpio_probe_raw()
1059 mvchip->percpu_regs = in mvebu_gpio_probe_raw()
1060 devm_regmap_init_mmio(&pdev->dev, base, in mvebu_gpio_probe_raw()
1062 if (IS_ERR(mvchip->percpu_regs)) in mvebu_gpio_probe_raw()
1063 return PTR_ERR(mvchip->percpu_regs); in mvebu_gpio_probe_raw()
1072 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); in mvebu_gpio_probe_syscon()
1073 if (IS_ERR(mvchip->regs)) in mvebu_gpio_probe_syscon()
1074 return PTR_ERR(mvchip->regs); in mvebu_gpio_probe_syscon()
1076 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset)) in mvebu_gpio_probe_syscon()
1077 return -EINVAL; in mvebu_gpio_probe_syscon()
1086 struct device_node *np = pdev->dev.of_node; in mvebu_gpio_probe()
1092 int i, cpu, id; in mvebu_gpio_probe() local
1095 match = of_match_device(mvebu_gpio_of_match, &pdev->dev); in mvebu_gpio_probe()
1097 soc_variant = (unsigned long) match->data; in mvebu_gpio_probe()
1108 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), in mvebu_gpio_probe()
1111 return -ENOMEM; in mvebu_gpio_probe()
1115 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { in mvebu_gpio_probe()
1116 dev_err(&pdev->dev, "Missing ngpios OF property\n"); in mvebu_gpio_probe()
1117 return -ENODEV; in mvebu_gpio_probe()
1120 id = of_alias_get_id(pdev->dev.of_node, "gpio"); in mvebu_gpio_probe()
1122 dev_err(&pdev->dev, "Couldn't get OF id\n"); in mvebu_gpio_probe()
1126 mvchip->clk = devm_clk_get(&pdev->dev, NULL); in mvebu_gpio_probe()
1128 if (!IS_ERR(mvchip->clk)) in mvebu_gpio_probe()
1129 clk_prepare_enable(mvchip->clk); in mvebu_gpio_probe()
1131 mvchip->soc_variant = soc_variant; in mvebu_gpio_probe()
1132 mvchip->chip.label = dev_name(&pdev->dev); in mvebu_gpio_probe()
1133 mvchip->chip.parent = &pdev->dev; in mvebu_gpio_probe()
1134 mvchip->chip.request = gpiochip_generic_request; in mvebu_gpio_probe()
1135 mvchip->chip.free = gpiochip_generic_free; in mvebu_gpio_probe()
1136 mvchip->chip.get_direction = mvebu_gpio_get_direction; in mvebu_gpio_probe()
1137 mvchip->chip.direction_input = mvebu_gpio_direction_input; in mvebu_gpio_probe()
1138 mvchip->chip.get = mvebu_gpio_get; in mvebu_gpio_probe()
1139 mvchip->chip.direction_output = mvebu_gpio_direction_output; in mvebu_gpio_probe()
1140 mvchip->chip.set = mvebu_gpio_set; in mvebu_gpio_probe()
1142 mvchip->chip.to_irq = mvebu_gpio_to_irq; in mvebu_gpio_probe()
1143 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; in mvebu_gpio_probe()
1144 mvchip->chip.ngpio = ngpios; in mvebu_gpio_probe()
1145 mvchip->chip.can_sleep = false; in mvebu_gpio_probe()
1146 mvchip->chip.of_node = np; in mvebu_gpio_probe()
1147 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; in mvebu_gpio_probe()
1163 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1164 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1165 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1166 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1167 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1168 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1171 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); in mvebu_gpio_probe()
1172 for (cpu = 0; cpu < 2; cpu++) { in mvebu_gpio_probe()
1173 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1174 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0); in mvebu_gpio_probe()
1175 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1176 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0); in mvebu_gpio_probe()
1180 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); in mvebu_gpio_probe()
1181 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); in mvebu_gpio_probe()
1182 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); in mvebu_gpio_probe()
1183 for (cpu = 0; cpu < 4; cpu++) { in mvebu_gpio_probe()
1184 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1185 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0); in mvebu_gpio_probe()
1186 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1187 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0); in mvebu_gpio_probe()
1188 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1189 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0); in mvebu_gpio_probe()
1196 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); in mvebu_gpio_probe()
1209 mvchip->domain = in mvebu_gpio_probe()
1211 if (!mvchip->domain) { in mvebu_gpio_probe()
1212 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", in mvebu_gpio_probe()
1213 mvchip->chip.label); in mvebu_gpio_probe()
1214 err = -ENODEV; in mvebu_gpio_probe()
1219 mvchip->domain, ngpios, 2, np->name, handle_level_irq, in mvebu_gpio_probe()
1222 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", in mvebu_gpio_probe()
1223 mvchip->chip.label); in mvebu_gpio_probe()
1231 gc = irq_get_domain_generic_chip(mvchip->domain, 0); in mvebu_gpio_probe()
1232 gc->private = mvchip; in mvebu_gpio_probe()
1233 ct = &gc->chip_types[0]; in mvebu_gpio_probe()
1234 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; in mvebu_gpio_probe()
1235 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; in mvebu_gpio_probe()
1236 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; in mvebu_gpio_probe()
1237 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; in mvebu_gpio_probe()
1238 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1240 ct = &gc->chip_types[1]; in mvebu_gpio_probe()
1241 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; in mvebu_gpio_probe()
1242 ct->chip.irq_ack = mvebu_gpio_irq_ack; in mvebu_gpio_probe()
1243 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; in mvebu_gpio_probe()
1244 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; in mvebu_gpio_probe()
1245 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; in mvebu_gpio_probe()
1246 ct->handler = handle_edge_irq; in mvebu_gpio_probe()
1247 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1266 irq_domain_remove(mvchip->domain); in mvebu_gpio_probe()
1268 pwmchip_remove(&mvchip->mvpwm->chip); in mvebu_gpio_probe()
1275 .name = "mvebu-gpio",