Lines Matching refs:DSSERR
167 DSSERR("illegal DSS PLL ID %d\n", pll->id); in dss_ctrl_pll_enable()
195 DSSERR("error in PLL mux config for LCD\n"); in dss_ctrl_pll_set_control_mux()
211 DSSERR("error in PLL mux config for LCD2\n"); in dss_ctrl_pll_set_control_mux()
227 DSSERR("error in PLL mux config for LCD3\n"); in dss_ctrl_pll_set_control_mux()
233 DSSERR("error in PLL mux config\n"); in dss_ctrl_pll_set_control_mux()
279 DSSERR("PLL lock request timed out\n"); in dss_sdi_enable()
291 DSSERR("PLL lock timed out\n"); in dss_sdi_enable()
302 DSSERR("SDI reset timed out\n"); in dss_sdi_enable()
826 DSSERR("can't get clock fck\n"); in dss_get_clocks()
835 DSSERR("Failed to get %s\n", in dss_get_clocks()
1265 DSSERR("can't get DPLL VDDA regulator\n"); in dss_video_pll_probe()