Lines Matching refs:cik
2331 u32 *tile = rdev->config.cik.tile_mode_array; in cik_tiling_mode_table_init()
2332 u32 *macrotile = rdev->config.cik.macrotile_mode_array; in cik_tiling_mode_table_init()
2334 ARRAY_SIZE(rdev->config.cik.tile_mode_array); in cik_tiling_mode_table_init()
2336 ARRAY_SIZE(rdev->config.cik.macrotile_mode_array); in cik_tiling_mode_table_init()
2339 u32 num_rbs = rdev->config.cik.max_backends_per_se * in cik_tiling_mode_table_init()
2340 rdev->config.cik.max_shader_engines; in cik_tiling_mode_table_init()
2342 switch (rdev->config.cik.mem_row_size_in_kb) { in cik_tiling_mode_table_init()
2355 num_pipe_configs = rdev->config.cik.max_tile_pipes; in cik_tiling_mode_table_init()
3139 rdev->config.cik.backend_enable_mask = enabled_rbs; in cik_setup_rb()
3188 rdev->config.cik.max_shader_engines = 2; in cik_gpu_init()
3189 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()
3190 rdev->config.cik.max_cu_per_sh = 7; in cik_gpu_init()
3191 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3192 rdev->config.cik.max_backends_per_se = 2; in cik_gpu_init()
3193 rdev->config.cik.max_texture_channel_caches = 4; in cik_gpu_init()
3194 rdev->config.cik.max_gprs = 256; in cik_gpu_init()
3195 rdev->config.cik.max_gs_threads = 32; in cik_gpu_init()
3196 rdev->config.cik.max_hw_contexts = 8; in cik_gpu_init()
3198 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20; in cik_gpu_init()
3199 rdev->config.cik.sc_prim_fifo_size_backend = 0x100; in cik_gpu_init()
3200 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30; in cik_gpu_init()
3201 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130; in cik_gpu_init()
3205 rdev->config.cik.max_shader_engines = 4; in cik_gpu_init()
3206 rdev->config.cik.max_tile_pipes = 16; in cik_gpu_init()
3207 rdev->config.cik.max_cu_per_sh = 11; in cik_gpu_init()
3208 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3209 rdev->config.cik.max_backends_per_se = 4; in cik_gpu_init()
3210 rdev->config.cik.max_texture_channel_caches = 16; in cik_gpu_init()
3211 rdev->config.cik.max_gprs = 256; in cik_gpu_init()
3212 rdev->config.cik.max_gs_threads = 32; in cik_gpu_init()
3213 rdev->config.cik.max_hw_contexts = 8; in cik_gpu_init()
3215 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20; in cik_gpu_init()
3216 rdev->config.cik.sc_prim_fifo_size_backend = 0x100; in cik_gpu_init()
3217 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30; in cik_gpu_init()
3218 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130; in cik_gpu_init()
3222 rdev->config.cik.max_shader_engines = 1; in cik_gpu_init()
3223 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()
3224 rdev->config.cik.max_cu_per_sh = 8; in cik_gpu_init()
3225 rdev->config.cik.max_backends_per_se = 2; in cik_gpu_init()
3226 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3227 rdev->config.cik.max_texture_channel_caches = 4; in cik_gpu_init()
3228 rdev->config.cik.max_gprs = 256; in cik_gpu_init()
3229 rdev->config.cik.max_gs_threads = 16; in cik_gpu_init()
3230 rdev->config.cik.max_hw_contexts = 8; in cik_gpu_init()
3232 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20; in cik_gpu_init()
3233 rdev->config.cik.sc_prim_fifo_size_backend = 0x100; in cik_gpu_init()
3234 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30; in cik_gpu_init()
3235 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130; in cik_gpu_init()
3241 rdev->config.cik.max_shader_engines = 1; in cik_gpu_init()
3242 rdev->config.cik.max_tile_pipes = 2; in cik_gpu_init()
3243 rdev->config.cik.max_cu_per_sh = 2; in cik_gpu_init()
3244 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3245 rdev->config.cik.max_backends_per_se = 1; in cik_gpu_init()
3246 rdev->config.cik.max_texture_channel_caches = 2; in cik_gpu_init()
3247 rdev->config.cik.max_gprs = 256; in cik_gpu_init()
3248 rdev->config.cik.max_gs_threads = 16; in cik_gpu_init()
3249 rdev->config.cik.max_hw_contexts = 8; in cik_gpu_init()
3251 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20; in cik_gpu_init()
3252 rdev->config.cik.sc_prim_fifo_size_backend = 0x100; in cik_gpu_init()
3253 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30; in cik_gpu_init()
3254 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130; in cik_gpu_init()
3277 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes; in cik_gpu_init()
3278 rdev->config.cik.mem_max_burst_length_bytes = 256; in cik_gpu_init()
3280 rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in cik_gpu_init()
3281 if (rdev->config.cik.mem_row_size_in_kb > 4) in cik_gpu_init()
3282 rdev->config.cik.mem_row_size_in_kb = 4; in cik_gpu_init()
3284 rdev->config.cik.shader_engine_tile_size = 32; in cik_gpu_init()
3285 rdev->config.cik.num_gpus = 1; in cik_gpu_init()
3286 rdev->config.cik.multi_gpu_tile_size = 64; in cik_gpu_init()
3290 switch (rdev->config.cik.mem_row_size_in_kb) { in cik_gpu_init()
3310 rdev->config.cik.tile_config = 0; in cik_gpu_init()
3311 switch (rdev->config.cik.num_tile_pipes) { in cik_gpu_init()
3313 rdev->config.cik.tile_config |= (0 << 0); in cik_gpu_init()
3316 rdev->config.cik.tile_config |= (1 << 0); in cik_gpu_init()
3319 rdev->config.cik.tile_config |= (2 << 0); in cik_gpu_init()
3324 rdev->config.cik.tile_config |= (3 << 0); in cik_gpu_init()
3327 rdev->config.cik.tile_config |= in cik_gpu_init()
3329 rdev->config.cik.tile_config |= in cik_gpu_init()
3331 rdev->config.cik.tile_config |= in cik_gpu_init()
3345 cik_setup_rb(rdev, rdev->config.cik.max_shader_engines, in cik_gpu_init()
3346 rdev->config.cik.max_sh_per_se, in cik_gpu_init()
3347 rdev->config.cik.max_backends_per_se); in cik_gpu_init()
3349 rdev->config.cik.active_cus = 0; in cik_gpu_init()
3350 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) { in cik_gpu_init()
3351 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_gpu_init()
3352 rdev->config.cik.active_cus += in cik_gpu_init()
3386 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) | in cik_gpu_init()
3387 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) | in cik_gpu_init()
3388 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) | in cik_gpu_init()
3389 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size))); in cik_gpu_init()
3987 WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1); in cik_cp_gfx_start()
5797 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) { in cik_wait_for_rlc_serdes()
5798 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_wait_for_rlc_serdes()
6550 for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) { in cik_get_cu_active_bitmap()
6564 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) { in cik_init_ao_cu_mask()
6565 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_init_ao_cu_mask()
6569 for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) { in cik_init_ao_cu_mask()
7300 rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS); in cik_irq_ack()
7301 rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in cik_irq_ack()
7302 rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); in cik_irq_ack()
7303 rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); in cik_irq_ack()
7304 rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); in cik_irq_ack()
7305 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); in cik_irq_ack()
7306 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6); in cik_irq_ack()
7308 rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7310 rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7313 rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7315 rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7319 rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7321 rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7325 if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED) in cik_irq_ack()
7328 if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED) in cik_irq_ack()
7331 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) in cik_irq_ack()
7333 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) in cik_irq_ack()
7335 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT) in cik_irq_ack()
7337 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT) in cik_irq_ack()
7341 if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED) in cik_irq_ack()
7344 if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED) in cik_irq_ack()
7347 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) in cik_irq_ack()
7349 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) in cik_irq_ack()
7351 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) in cik_irq_ack()
7353 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) in cik_irq_ack()
7358 if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED) in cik_irq_ack()
7361 if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED) in cik_irq_ack()
7364 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) in cik_irq_ack()
7366 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) in cik_irq_ack()
7368 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) in cik_irq_ack()
7370 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) in cik_irq_ack()
7374 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) { in cik_irq_ack()
7379 if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) { in cik_irq_ack()
7384 if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) { in cik_irq_ack()
7389 if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) { in cik_irq_ack()
7394 if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) { in cik_irq_ack()
7399 if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) { in cik_irq_ack()
7404 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) { in cik_irq_ack()
7409 if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT) { in cik_irq_ack()
7414 if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { in cik_irq_ack()
7419 if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { in cik_irq_ack()
7424 if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { in cik_irq_ack()
7429 if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { in cik_irq_ack()
7595 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)) in cik_irq_process()
7605 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in cik_irq_process()
7610 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)) in cik_irq_process()
7613 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT; in cik_irq_process()
7625 if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT)) in cik_irq_process()
7635 rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; in cik_irq_process()
7640 if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT)) in cik_irq_process()
7643 rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; in cik_irq_process()
7655 if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)) in cik_irq_process()
7665 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; in cik_irq_process()
7670 if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)) in cik_irq_process()
7673 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; in cik_irq_process()
7685 if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)) in cik_irq_process()
7695 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; in cik_irq_process()
7700 if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)) in cik_irq_process()
7703 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; in cik_irq_process()
7715 if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)) in cik_irq_process()
7725 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; in cik_irq_process()
7730 if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)) in cik_irq_process()
7733 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; in cik_irq_process()
7745 if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)) in cik_irq_process()
7755 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; in cik_irq_process()
7760 if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)) in cik_irq_process()
7763 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; in cik_irq_process()
7785 if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT)) in cik_irq_process()
7788 rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT; in cik_irq_process()
7794 if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT)) in cik_irq_process()
7797 rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT; in cik_irq_process()
7803 if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT)) in cik_irq_process()
7806 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; in cik_irq_process()
7812 if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT)) in cik_irq_process()
7815 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; in cik_irq_process()
7821 if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT)) in cik_irq_process()
7824 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; in cik_irq_process()
7830 if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT)) in cik_irq_process()
7833 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; in cik_irq_process()
7839 if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT)) in cik_irq_process()
7842 rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT; in cik_irq_process()
7848 if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT)) in cik_irq_process()
7851 rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; in cik_irq_process()
7857 if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT)) in cik_irq_process()
7860 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; in cik_irq_process()
7866 if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT)) in cik_irq_process()
7869 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; in cik_irq_process()
7875 if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT)) in cik_irq_process()
7878 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; in cik_irq_process()
7884 if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT)) in cik_irq_process()
7887 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; in cik_irq_process()