Lines Matching refs:rlc
4115 if (rdev->rlc.save_restore_obj) { in sumo_rlc_fini()
4116 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_fini()
4119 radeon_bo_unpin(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4120 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4122 radeon_bo_unref(&rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4123 rdev->rlc.save_restore_obj = NULL; in sumo_rlc_fini()
4127 if (rdev->rlc.clear_state_obj) { in sumo_rlc_fini()
4128 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_fini()
4131 radeon_bo_unpin(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4132 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4134 radeon_bo_unref(&rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4135 rdev->rlc.clear_state_obj = NULL; in sumo_rlc_fini()
4139 if (rdev->rlc.cp_table_obj) { in sumo_rlc_fini()
4140 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false); in sumo_rlc_fini()
4143 radeon_bo_unpin(rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4144 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4146 radeon_bo_unref(&rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4147 rdev->rlc.cp_table_obj = NULL; in sumo_rlc_fini()
4163 src_ptr = rdev->rlc.reg_list; in sumo_rlc_init()
4164 dws = rdev->rlc.reg_list_size; in sumo_rlc_init()
4168 cs_data = rdev->rlc.cs_data; in sumo_rlc_init()
4172 if (rdev->rlc.save_restore_obj == NULL) { in sumo_rlc_init()
4175 NULL, &rdev->rlc.save_restore_obj); in sumo_rlc_init()
4182 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_init()
4187 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4188 &rdev->rlc.save_restore_gpu_addr); in sumo_rlc_init()
4190 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4196 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr); in sumo_rlc_init()
4203 dst_ptr = rdev->rlc.sr_ptr; in sumo_rlc_init()
4206 for (i = 0; i < rdev->rlc.reg_list_size; i++) in sumo_rlc_init()
4226 radeon_bo_kunmap(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4227 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4233 rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev); in sumo_rlc_init()
4235 rdev->rlc.clear_state_size = si_get_csb_size(rdev); in sumo_rlc_init()
4236 dws = rdev->rlc.clear_state_size + (256 / 4); in sumo_rlc_init()
4248 rdev->rlc.clear_state_size = dws; in sumo_rlc_init()
4251 if (rdev->rlc.clear_state_obj == NULL) { in sumo_rlc_init()
4254 NULL, &rdev->rlc.clear_state_obj); in sumo_rlc_init()
4261 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_init()
4266 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4267 &rdev->rlc.clear_state_gpu_addr); in sumo_rlc_init()
4269 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4275 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr); in sumo_rlc_init()
4282 dst_ptr = rdev->rlc.cs_ptr; in sumo_rlc_init()
4286 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; in sumo_rlc_init()
4289 dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size); in sumo_rlc_init()
4293 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); in sumo_rlc_init()
4322 radeon_bo_kunmap(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4323 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4326 if (rdev->rlc.cp_table_size) { in sumo_rlc_init()
4327 if (rdev->rlc.cp_table_obj == NULL) { in sumo_rlc_init()
4328 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size, in sumo_rlc_init()
4331 NULL, &rdev->rlc.cp_table_obj); in sumo_rlc_init()
4339 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false); in sumo_rlc_init()
4345 r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4346 &rdev->rlc.cp_table_gpu_addr); in sumo_rlc_init()
4348 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4353 r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr); in sumo_rlc_init()
4362 radeon_bo_kunmap(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4363 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4412 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in evergreen_rlc_resume()
4413 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
5035 rdev->rlc.reg_list = sumo_rlc_save_restore_register_list; in evergreen_startup()
5036 rdev->rlc.reg_list_size = in evergreen_startup()
5038 rdev->rlc.cs_data = evergreen_cs_data; in evergreen_startup()