Lines Matching +full:0 +full:x22c
30 #define CG_CGTT_LOCAL_0 0x0
31 #define CG_CGTT_LOCAL_1 0x1
34 #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000
35 # define STATE_VALID(x) ((x) << 0)
36 # define STATE_VALID_MASK (0xff << 0)
37 # define STATE_VALID_SHIFT 0
39 # define CLK_DIVIDER_MASK (0xff << 8)
42 # define VID_MASK (0xff << 16)
45 # define LVRT_MASK (0xff << 24)
47 #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004
48 # define DS_DIV(x) ((x) << 0)
49 # define DS_DIV_MASK (0xff << 0)
50 # define DS_DIV_SHIFT 0
52 # define DS_SH_DIV_MASK (0xff << 8)
55 # define DISPLAY_WM_MASK (0xff << 16)
58 # define VCE_WM_MASK (0xff << 24)
61 #define SMU_SCLK_DPM_STATE_0_CNTL_3 0x1f00c
62 # define GNB_SLOW(x) ((x) << 0)
63 # define GNB_SLOW_MASK (0xff << 0)
64 # define GNB_SLOW_SHIFT 0
66 # define FORCE_NBPS1_MASK (0xff << 8)
68 #define SMU_SCLK_DPM_STATE_0_AT 0x1f010
69 # define AT(x) ((x) << 0)
70 # define AT_MASK (0xff << 0)
71 # define AT_SHIFT 0
73 #define SMU_SCLK_DPM_STATE_0_PG_CNTL 0x1f014
75 # define PD_SCLK_DIVIDER_MASK (0xff << 16)
78 #define SMU_SCLK_DPM_STATE_1_CNTL_0 0x1f020
80 #define SMU_SCLK_DPM_CNTL 0x1f100
81 # define SCLK_DPM_EN(x) ((x) << 0)
82 # define SCLK_DPM_EN_MASK (0xff << 0)
83 # define SCLK_DPM_EN_SHIFT 0
85 # define SCLK_DPM_BOOT_STATE_MASK (0xff << 16)
88 # define VOLTAGE_CHG_EN_MASK (0xff << 24)
91 #define SMU_SCLK_DPM_TT_CNTL 0x1f108
92 # define SCLK_TT_EN(x) ((x) << 0)
93 # define SCLK_TT_EN_MASK (0xff << 0)
94 # define SCLK_TT_EN_SHIFT 0
95 #define SMU_SCLK_DPM_TTT 0x1f10c
96 # define LT(x) ((x) << 0)
97 # define LT_MASK (0xffff << 0)
98 # define LT_SHIFT 0
100 # define HT_MASK (0xffff << 16)
103 #define SMU_UVD_DPM_STATES 0x1f1a0
104 #define SMU_UVD_DPM_CNTL 0x1f1a4
106 #define SMU_S_PG_CNTL 0x1f118
108 # define DS_PG_EN_MASK (0xff << 16)
111 #define GFX_POWER_GATING_CNTL 0x1f38c
112 # define PDS_DIV(x) ((x) << 0)
113 # define PDS_DIV_MASK (0xff << 0)
114 # define PDS_DIV_SHIFT 0
116 # define SSSD_MASK (0xff << 8)
119 #define PM_CONFIG 0x1f428
122 #define PM_I_CNTL_1 0x1f464
123 # define SCLK_DPM(x) ((x) << 0)
124 # define SCLK_DPM_MASK (0xff << 0)
125 # define SCLK_DPM_SHIFT 0
127 # define DS_PG_CNTL_MASK (0xff << 16)
129 #define PM_TP 0x1f468
131 #define NB_PSTATE_CONFIG 0x1f5f8
132 # define Dpm0PgNbPsLo(x) ((x) << 0)
133 # define Dpm0PgNbPsLo_MASK (3 << 0)
134 # define Dpm0PgNbPsLo_SHIFT 0
145 #define DC_CAC_VALUE 0x1f908
147 #define GPU_CAC_AVRG_CNTL 0x1f920
148 # define WINDOW_SIZE(x) ((x) << 0)
149 # define WINDOW_SIZE_MASK (0xff << 0)
150 # define WINDOW_SIZE_SHIFT 0
152 #define CC_SMU_MISC_FUSES 0xe0001004
154 # define MinSClkDid_MASK (0x7f << 2)
157 #define CC_SMU_TST_EFUSE1_MISC 0xe000101c
162 #define SMU_SCRATCH_A 0xe0003024
164 #define SMU_SCRATCH0 0xe0003040
167 #define SMC_INT_REQ 0x220
169 #define SMC_MESSAGE_0 0x22c
170 #define SMC_RESP_0 0x230
172 #define GENERAL_PWRMGT 0x670
173 # define GLOBAL_PWRMGT_EN (1 << 0)
175 #define SCLK_PWRMGT_CNTL 0x678
183 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x684
184 # define TARGET_STATE(x) ((x) << 0)
185 # define TARGET_STATE_MASK (0xf << 0)
186 # define TARGET_STATE_SHIFT 0
188 # define CURRENT_STATE_MASK (0xf << 4)
191 #define CG_GIPOTS 0x6d8
193 # define CG_GIPOT_MASK (0xffff << 16)
196 #define CG_PG_CTRL 0x6e0
197 # define SP(x) ((x) << 0)
198 # define SP_MASK (0xffff << 0)
199 # define SP_SHIFT 0
201 # define SU_MASK (0xffff << 16)
204 #define CG_MISC_REG 0x708
206 #define CG_THERMAL_INT_CTRL 0x738
207 # define DIG_THERM_INTH(x) ((x) << 0)
208 # define DIG_THERM_INTH_MASK (0xff << 0)
209 # define DIG_THERM_INTH_SHIFT 0
211 # define DIG_THERM_INTL_MASK (0xff << 8)
216 #define CG_CG_VOLTAGE_CNTL 0x770
219 #define HW_REV 0x5564
220 # define ATI_REV_ID_MASK (0xf << 28)
222 /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */
224 #define CGTS_SM_CTRL_REG 0x9150
226 #define GB_ADDR_CONFIG 0x98f8