Lines Matching refs:dispc
310 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val) in dispc_write() argument
312 iowrite32(val, dispc->base_common + reg); in dispc_write()
315 static u32 dispc_read(struct dispc_device *dispc, u16 reg) in dispc_read() argument
317 return ioread32(dispc->base_common + reg); in dispc_read()
321 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) in dispc_vid_write() argument
323 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
328 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) in dispc_vid_read() argument
330 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
335 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport, in dispc_ovr_write() argument
338 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_write()
343 static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) in dispc_ovr_read() argument
345 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_read()
350 static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_write() argument
353 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_write()
358 static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) in dispc_vp_read() argument
360 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_read()
390 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) in REG_GET() argument
392 return FLD_GET(dispc_read(dispc, idx), start, end); in REG_GET()
395 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, in REG_FLD_MOD() argument
398 dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val, in REG_FLD_MOD()
402 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, in VID_REG_GET() argument
405 return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end); in VID_REG_GET()
408 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx, in VID_REG_FLD_MOD() argument
411 dispc_vid_write(dispc, hw_plane, idx, in VID_REG_FLD_MOD()
412 FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), in VID_REG_FLD_MOD()
416 static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, in VP_REG_GET() argument
419 return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end); in VP_REG_GET()
422 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val, in VP_REG_FLD_MOD() argument
425 dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), in VP_REG_FLD_MOD()
430 static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx, in OVR_REG_GET() argument
433 return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end); in OVR_REG_GET()
436 static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, in OVR_REG_FLD_MOD() argument
439 dispc_ovr_write(dispc, ovr, idx, in OVR_REG_FLD_MOD()
440 FLD_MOD(dispc_ovr_read(dispc, ovr, idx), in OVR_REG_FLD_MOD()
496 static dispc_irq_t dispc_k2g_vp_read_irqstatus(struct dispc_device *dispc, in dispc_k2g_vp_read_irqstatus() argument
499 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS); in dispc_k2g_vp_read_irqstatus()
504 static void dispc_k2g_vp_write_irqstatus(struct dispc_device *dispc, in dispc_k2g_vp_write_irqstatus() argument
509 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS, stat); in dispc_k2g_vp_write_irqstatus()
512 static dispc_irq_t dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc, in dispc_k2g_vid_read_irqstatus() argument
515 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS); in dispc_k2g_vid_read_irqstatus()
520 static void dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc, in dispc_k2g_vid_write_irqstatus() argument
525 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat); in dispc_k2g_vid_write_irqstatus()
528 static dispc_irq_t dispc_k2g_vp_read_irqenable(struct dispc_device *dispc, in dispc_k2g_vp_read_irqenable() argument
531 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE); in dispc_k2g_vp_read_irqenable()
536 static void dispc_k2g_vp_set_irqenable(struct dispc_device *dispc, in dispc_k2g_vp_set_irqenable() argument
541 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE, stat); in dispc_k2g_vp_set_irqenable()
544 static dispc_irq_t dispc_k2g_vid_read_irqenable(struct dispc_device *dispc, in dispc_k2g_vid_read_irqenable() argument
547 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE); in dispc_k2g_vid_read_irqenable()
552 static void dispc_k2g_vid_set_irqenable(struct dispc_device *dispc, in dispc_k2g_vid_set_irqenable() argument
557 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat); in dispc_k2g_vid_set_irqenable()
560 static void dispc_k2g_clear_irqstatus(struct dispc_device *dispc, in dispc_k2g_clear_irqstatus() argument
563 dispc_k2g_vp_write_irqstatus(dispc, 0, mask); in dispc_k2g_clear_irqstatus()
564 dispc_k2g_vid_write_irqstatus(dispc, 0, mask); in dispc_k2g_clear_irqstatus()
568 dispc_irq_t dispc_k2g_read_and_clear_irqstatus(struct dispc_device *dispc) in dispc_k2g_read_and_clear_irqstatus() argument
573 dispc_write(dispc, DISPC_IRQSTATUS, in dispc_k2g_read_and_clear_irqstatus()
574 dispc_read(dispc, DISPC_IRQSTATUS)); in dispc_k2g_read_and_clear_irqstatus()
576 stat |= dispc_k2g_vp_read_irqstatus(dispc, 0); in dispc_k2g_read_and_clear_irqstatus()
577 stat |= dispc_k2g_vid_read_irqstatus(dispc, 0); in dispc_k2g_read_and_clear_irqstatus()
579 dispc_k2g_clear_irqstatus(dispc, stat); in dispc_k2g_read_and_clear_irqstatus()
584 static dispc_irq_t dispc_k2g_read_irqenable(struct dispc_device *dispc) in dispc_k2g_read_irqenable() argument
588 stat |= dispc_k2g_vp_read_irqenable(dispc, 0); in dispc_k2g_read_irqenable()
589 stat |= dispc_k2g_vid_read_irqenable(dispc, 0); in dispc_k2g_read_irqenable()
595 void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) in dispc_k2g_set_irqenable() argument
597 dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc); in dispc_k2g_set_irqenable()
600 dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask); in dispc_k2g_set_irqenable()
602 dispc_k2g_vp_set_irqenable(dispc, 0, mask); in dispc_k2g_set_irqenable()
603 dispc_k2g_vid_set_irqenable(dispc, 0, mask); in dispc_k2g_set_irqenable()
605 dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7)); in dispc_k2g_set_irqenable()
608 dispc_k2g_read_irqenable(dispc); in dispc_k2g_set_irqenable()
611 static dispc_irq_t dispc_k3_vp_read_irqstatus(struct dispc_device *dispc, in dispc_k3_vp_read_irqstatus() argument
614 u32 stat = dispc_read(dispc, DISPC_VP_IRQSTATUS(hw_videoport)); in dispc_k3_vp_read_irqstatus()
619 static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc, in dispc_k3_vp_write_irqstatus() argument
624 dispc_write(dispc, DISPC_VP_IRQSTATUS(hw_videoport), stat); in dispc_k3_vp_write_irqstatus()
627 static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc, in dispc_k3_vid_read_irqstatus() argument
630 u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane)); in dispc_k3_vid_read_irqstatus()
635 static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc, in dispc_k3_vid_write_irqstatus() argument
640 dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat); in dispc_k3_vid_write_irqstatus()
643 static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc, in dispc_k3_vp_read_irqenable() argument
646 u32 stat = dispc_read(dispc, DISPC_VP_IRQENABLE(hw_videoport)); in dispc_k3_vp_read_irqenable()
651 static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc, in dispc_k3_vp_set_irqenable() argument
656 dispc_write(dispc, DISPC_VP_IRQENABLE(hw_videoport), stat); in dispc_k3_vp_set_irqenable()
659 static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc, in dispc_k3_vid_read_irqenable() argument
662 u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane)); in dispc_k3_vid_read_irqenable()
667 static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc, in dispc_k3_vid_set_irqenable() argument
672 dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat); in dispc_k3_vid_set_irqenable()
676 void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask) in dispc_k3_clear_irqstatus() argument
681 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_clear_irqstatus()
683 dispc_k3_vp_write_irqstatus(dispc, i, clearmask); in dispc_k3_clear_irqstatus()
687 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_clear_irqstatus()
689 dispc_k3_vid_write_irqstatus(dispc, i, clearmask); in dispc_k3_clear_irqstatus()
693 if (dispc->feat->subrev == DISPC_K2G) in dispc_k3_clear_irqstatus()
696 dispc_write(dispc, DISPC_IRQSTATUS, top_clear); in dispc_k3_clear_irqstatus()
699 dispc_read(dispc, DISPC_IRQSTATUS); in dispc_k3_clear_irqstatus()
703 dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc) in dispc_k3_read_and_clear_irqstatus() argument
708 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_and_clear_irqstatus()
709 status |= dispc_k3_vp_read_irqstatus(dispc, i); in dispc_k3_read_and_clear_irqstatus()
711 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_and_clear_irqstatus()
712 status |= dispc_k3_vid_read_irqstatus(dispc, i); in dispc_k3_read_and_clear_irqstatus()
714 dispc_k3_clear_irqstatus(dispc, status); in dispc_k3_read_and_clear_irqstatus()
719 static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc) in dispc_k3_read_irqenable() argument
724 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_irqenable()
725 enable |= dispc_k3_vp_read_irqenable(dispc, i); in dispc_k3_read_irqenable()
727 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_irqenable()
728 enable |= dispc_k3_vid_read_irqenable(dispc, i); in dispc_k3_read_irqenable()
733 static void dispc_k3_set_irqenable(struct dispc_device *dispc, in dispc_k3_set_irqenable() argument
740 old_mask = dispc_k3_read_irqenable(dispc); in dispc_k3_set_irqenable()
743 dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask); in dispc_k3_set_irqenable()
745 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_set_irqenable()
746 dispc_k3_vp_set_irqenable(dispc, i, mask); in dispc_k3_set_irqenable()
753 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_set_irqenable()
754 dispc_k3_vid_set_irqenable(dispc, i, mask); in dispc_k3_set_irqenable()
762 dispc_write(dispc, DISPC_IRQENABLE_SET, main_enable); in dispc_k3_set_irqenable()
765 dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable); in dispc_k3_set_irqenable()
768 dispc_read(dispc, DISPC_IRQENABLE_SET); in dispc_k3_set_irqenable()
771 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc) in dispc_read_and_clear_irqstatus() argument
773 switch (dispc->feat->subrev) { in dispc_read_and_clear_irqstatus()
775 return dispc_k2g_read_and_clear_irqstatus(dispc); in dispc_read_and_clear_irqstatus()
778 return dispc_k3_read_and_clear_irqstatus(dispc); in dispc_read_and_clear_irqstatus()
785 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) in dispc_set_irqenable() argument
787 switch (dispc->feat->subrev) { in dispc_set_irqenable()
789 dispc_k2g_set_irqenable(dispc, mask); in dispc_set_irqenable()
793 dispc_k3_set_irqenable(dispc, mask); in dispc_set_irqenable()
823 struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc, in dispc_vp_find_bus_fmt() argument
837 int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_bus_check() argument
843 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_bus_check()
846 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n", in dispc_vp_bus_check()
851 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI && in dispc_vp_bus_check()
853 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n", in dispc_vp_bus_check()
854 __func__, dispc->feat->vp_name[hw_videoport]); in dispc_vp_bus_check()
861 static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power) in dispc_oldi_tx_power() argument
865 if (WARN_ON(!dispc->oldi_io_ctrl)) in dispc_oldi_tx_power()
868 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, in dispc_oldi_tx_power()
870 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, in dispc_oldi_tx_power()
872 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, in dispc_oldi_tx_power()
874 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, in dispc_oldi_tx_power()
876 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, in dispc_oldi_tx_power()
880 static void dispc_set_num_datalines(struct dispc_device *dispc, in dispc_set_num_datalines() argument
903 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8); in dispc_set_num_datalines()
906 static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, in dispc_enable_oldi() argument
921 dev_warn(dispc->dev, "%s: %d port width not supported\n", in dispc_enable_oldi()
932 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); in dispc_enable_oldi()
934 while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) && in dispc_enable_oldi()
938 if (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS))) in dispc_enable_oldi()
939 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n", in dispc_enable_oldi()
943 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_prepare() argument
949 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_prepare()
955 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_prepare()
956 dispc_oldi_tx_power(dispc, true); in dispc_vp_prepare()
958 dispc_enable_oldi(dispc, hw_videoport, fmt); in dispc_vp_prepare()
962 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_enable() argument
971 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_enable()
977 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width); in dispc_vp_enable()
987 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, in dispc_vp_enable()
992 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, in dispc_vp_enable()
1014 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) in dispc_vp_enable()
1017 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, in dispc_vp_enable()
1026 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, in dispc_vp_enable()
1030 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); in dispc_vp_enable()
1033 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_disable() argument
1035 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0); in dispc_vp_disable()
1038 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_unprepare() argument
1040 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_unprepare()
1041 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0); in dispc_vp_unprepare()
1043 dispc_oldi_tx_power(dispc, false); in dispc_vp_unprepare()
1047 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_go_busy() argument
1049 return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5); in dispc_vp_go_busy()
1052 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_go() argument
1054 WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5)); in dispc_vp_go()
1055 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); in dispc_vp_go()
1098 static void dispc_vp_set_default_color(struct dispc_device *dispc, in dispc_vp_set_default_color() argument
1105 dispc_ovr_write(dispc, hw_videoport, in dispc_vp_set_default_color()
1107 dispc_ovr_write(dispc, hw_videoport, in dispc_vp_set_default_color()
1111 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, in dispc_vp_mode_valid() argument
1119 bus_type = dispc->feat->vp_bus_type[hw_videoport]; in dispc_vp_mode_valid()
1121 max_pclk = dispc->feat->max_pclk_khz[bus_type]; in dispc_vp_mode_valid()
1126 if (mode->clock < dispc->feat->min_pclk_khz) in dispc_vp_mode_valid()
1170 if (dispc->memory_bandwidth_limit) { in dispc_vp_mode_valid()
1178 if (dispc->memory_bandwidth_limit < bandwidth) in dispc_vp_mode_valid()
1185 int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_enable_clk() argument
1187 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]); in dispc_vp_enable_clk()
1190 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__, in dispc_vp_enable_clk()
1196 void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_disable_clk() argument
1198 clk_disable_unprepare(dispc->vp_clk[hw_videoport]); in dispc_vp_disable_clk()
1213 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_set_clk_rate() argument
1219 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); in dispc_vp_set_clk_rate()
1221 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", in dispc_vp_set_clk_rate()
1226 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]); in dispc_vp_set_clk_rate()
1229 dev_warn(dispc->dev, in dispc_vp_set_clk_rate()
1233 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n", in dispc_vp_set_clk_rate()
1234 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate); in dispc_vp_set_clk_rate()
1240 static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc, in dispc_k2g_ovr_set_plane() argument
1245 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION, in dispc_k2g_ovr_set_plane()
1249 static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc, in dispc_am65x_ovr_set_plane() argument
1253 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_am65x_ovr_set_plane()
1255 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_am65x_ovr_set_plane()
1257 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_am65x_ovr_set_plane()
1261 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, in dispc_j721e_ovr_set_plane() argument
1265 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_j721e_ovr_set_plane()
1267 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), in dispc_j721e_ovr_set_plane()
1269 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), in dispc_j721e_ovr_set_plane()
1273 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, in dispc_ovr_set_plane() argument
1276 switch (dispc->feat->subrev) { in dispc_ovr_set_plane()
1278 dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport, in dispc_ovr_set_plane()
1282 dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, in dispc_ovr_set_plane()
1286 dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport, in dispc_ovr_set_plane()
1295 void dispc_ovr_enable_layer(struct dispc_device *dispc, in dispc_ovr_enable_layer() argument
1298 if (dispc->feat->subrev == DISPC_K2G) in dispc_ovr_enable_layer()
1301 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_ovr_enable_layer()
1384 static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, in dispc_k2g_vid_write_csc() argument
1399 dev_warn(dispc->dev, "%s: No post offset support for %s\n", in dispc_k2g_vid_write_csc()
1403 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], in dispc_k2g_vid_write_csc()
1407 static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, in dispc_k3_vid_write_csc() argument
1422 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], in dispc_k3_vid_write_csc()
1504 static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane, in dispc_vid_csc_setup() argument
1511 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n", in dispc_vid_csc_setup()
1516 if (dispc->feat->subrev == DISPC_K2G) in dispc_vid_csc_setup()
1517 dispc_k2g_vid_write_csc(dispc, hw_plane, coef); in dispc_vid_csc_setup()
1519 dispc_k3_vid_write_csc(dispc, hw_plane, coef); in dispc_vid_csc_setup()
1522 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, in dispc_vid_csc_enable() argument
1525 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9); in dispc_vid_csc_enable()
1542 static void dispc_vid_write_fir_coefs(struct dispc_device *dispc, in dispc_vid_write_fir_coefs() argument
1566 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__); in dispc_vid_write_fir_coefs()
1574 dispc_vid_write(dispc, hw_plane, reg, c0); in dispc_vid_write_fir_coefs()
1586 dispc_vid_write(dispc, hw_plane, reg, c12); in dispc_vid_write_fir_coefs()
1611 static int dispc_vid_calc_scaling(struct dispc_device *dispc, in dispc_vid_calc_scaling() argument
1616 const struct dispc_features_scaling *f = &dispc->feat->scaling; in dispc_vid_calc_scaling()
1665 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1678 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1695 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1716 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1734 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1750 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1758 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1765 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc, in dispc_vid_calc_scaling()
1769 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc, in dispc_vid_calc_scaling()
1775 static void dispc_vid_set_scaling(struct dispc_device *dispc, in dispc_vid_set_scaling() argument
1781 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_vid_set_scaling()
1785 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_vid_set_scaling()
1793 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_vid_set_scaling()
1798 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, in dispc_vid_set_scaling()
1800 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1805 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2, in dispc_vid_set_scaling()
1807 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1814 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc); in dispc_vid_set_scaling()
1815 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1821 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc); in dispc_vid_set_scaling()
1822 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1875 static void dispc_plane_set_pixel_format(struct dispc_device *dispc, in dispc_plane_set_pixel_format() argument
1882 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_plane_set_pixel_format()
1892 const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len) in dispc_plane_formats() argument
1894 WARN_ON(!dispc->fourccs); in dispc_plane_formats()
1896 *len = dispc->num_fourccs; in dispc_plane_formats()
1898 return dispc->fourccs; in dispc_plane_formats()
1914 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, in dispc_plane_check() argument
1918 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_check()
1928 dev_dbg(dispc->dev, in dispc_plane_check()
1938 dev_dbg(dispc->dev, in dispc_plane_check()
1945 ret = dispc_vid_calc_scaling(dispc, state, &scaling, false); in dispc_plane_check()
1985 int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, in dispc_plane_setup() argument
1989 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_setup()
1996 dispc_vid_calc_scaling(dispc, state, &scale, lite); in dispc_plane_setup()
1998 dispc_plane_set_pixel_format(dispc, hw_plane, fourcc); in dispc_plane_setup()
2000 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, paddr & 0xffffffff); in dispc_plane_setup()
2001 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)paddr >> 32); in dispc_plane_setup()
2002 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, paddr & 0xffffffff); in dispc_plane_setup()
2003 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)paddr >> 32); in dispc_plane_setup()
2005 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE, in dispc_plane_setup()
2010 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, in dispc_plane_setup()
2013 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, in dispc_plane_setup()
2016 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC, in dispc_plane_setup()
2026 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2028 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2030 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2032 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2035 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV, in dispc_plane_setup()
2042 dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE, in dispc_plane_setup()
2046 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc); in dispc_plane_setup()
2051 dispc_vid_csc_setup(dispc, hw_plane, state); in dispc_plane_setup()
2052 dispc_vid_csc_enable(dispc, hw_plane, true); in dispc_plane_setup()
2054 dispc_vid_csc_enable(dispc, hw_plane, false); in dispc_plane_setup()
2057 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, in dispc_plane_setup()
2061 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, in dispc_plane_setup()
2064 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, in dispc_plane_setup()
2070 int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) in dispc_plane_enable() argument
2072 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); in dispc_plane_enable()
2077 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane) in dispc_vid_get_fifo_size() argument
2079 return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0); in dispc_vid_get_fifo_size()
2082 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, in dispc_vid_set_mflag_threshold() argument
2085 dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, in dispc_vid_set_mflag_threshold()
2089 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, in dispc_vid_set_buf_threshold() argument
2092 dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, in dispc_vid_set_buf_threshold()
2096 static void dispc_k2g_plane_init(struct dispc_device *dispc) in dispc_k2g_plane_init() argument
2100 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k2g_plane_init()
2103 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); in dispc_k2g_plane_init()
2105 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); in dispc_k2g_plane_init()
2107 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k2g_plane_init()
2108 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); in dispc_k2g_plane_init()
2121 dev_dbg(dispc->dev, in dispc_k2g_plane_init()
2123 dispc->feat->vid_name[hw_plane], in dispc_k2g_plane_init()
2129 dispc_vid_set_buf_threshold(dispc, hw_plane, in dispc_k2g_plane_init()
2131 dispc_vid_set_mflag_threshold(dispc, hw_plane, in dispc_k2g_plane_init()
2134 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); in dispc_k2g_plane_init()
2141 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, in dispc_k2g_plane_init()
2146 static void dispc_k3_plane_init(struct dispc_device *dispc) in dispc_k3_plane_init() argument
2152 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k3_plane_init()
2154 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0); in dispc_k3_plane_init()
2155 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3); in dispc_k3_plane_init()
2158 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); in dispc_k3_plane_init()
2160 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); in dispc_k3_plane_init()
2162 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k3_plane_init()
2163 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); in dispc_k3_plane_init()
2176 dev_dbg(dispc->dev, in dispc_k3_plane_init()
2178 dispc->feat->vid_name[hw_plane], in dispc_k3_plane_init()
2184 dispc_vid_set_buf_threshold(dispc, hw_plane, in dispc_k3_plane_init()
2186 dispc_vid_set_mflag_threshold(dispc, hw_plane, in dispc_k3_plane_init()
2189 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); in dispc_k3_plane_init()
2192 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, in dispc_k3_plane_init()
2197 static void dispc_plane_init(struct dispc_device *dispc) in dispc_plane_init() argument
2199 switch (dispc->feat->subrev) { in dispc_plane_init()
2201 dispc_k2g_plane_init(dispc); in dispc_plane_init()
2205 dispc_k3_plane_init(dispc); in dispc_plane_init()
2212 static void dispc_vp_init(struct dispc_device *dispc) in dispc_vp_init() argument
2216 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_vp_init()
2219 for (i = 0; i < dispc->feat->num_vps; i++) in dispc_vp_init()
2220 VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2); in dispc_vp_init()
2223 static void dispc_initial_config(struct dispc_device *dispc) in dispc_initial_config() argument
2225 dispc_plane_init(dispc); in dispc_initial_config()
2226 dispc_vp_init(dispc); in dispc_initial_config()
2229 if (dispc->feat->subrev == DISPC_J721E) { in dispc_initial_config()
2230 dispc_write(dispc, DISPC_CONNECTIONS, in dispc_initial_config()
2237 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, in dispc_k2g_vp_write_gamma_table() argument
2240 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_k2g_vp_write_gamma_table()
2241 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_k2g_vp_write_gamma_table()
2244 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_k2g_vp_write_gamma_table()
2246 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_k2g_vp_write_gamma_table()
2254 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_GAMMA_TABLE, in dispc_k2g_vp_write_gamma_table()
2259 static void dispc_am65x_vp_write_gamma_table(struct dispc_device *dispc, in dispc_am65x_vp_write_gamma_table() argument
2262 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_am65x_vp_write_gamma_table()
2263 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_am65x_vp_write_gamma_table()
2266 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_am65x_vp_write_gamma_table()
2268 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_am65x_vp_write_gamma_table()
2276 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v); in dispc_am65x_vp_write_gamma_table()
2280 static void dispc_j721e_vp_write_gamma_table(struct dispc_device *dispc, in dispc_j721e_vp_write_gamma_table() argument
2283 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_j721e_vp_write_gamma_table()
2284 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_j721e_vp_write_gamma_table()
2287 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_j721e_vp_write_gamma_table()
2289 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT)) in dispc_j721e_vp_write_gamma_table()
2298 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v); in dispc_j721e_vp_write_gamma_table()
2302 static void dispc_vp_write_gamma_table(struct dispc_device *dispc, in dispc_vp_write_gamma_table() argument
2305 switch (dispc->feat->subrev) { in dispc_vp_write_gamma_table()
2307 dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); in dispc_vp_write_gamma_table()
2310 dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); in dispc_vp_write_gamma_table()
2313 dispc_j721e_vp_write_gamma_table(dispc, hw_videoport); in dispc_vp_write_gamma_table()
2326 static void dispc_vp_set_gamma(struct dispc_device *dispc, in dispc_vp_set_gamma() argument
2331 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_vp_set_gamma()
2332 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_vp_set_gamma()
2336 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", in dispc_vp_set_gamma()
2339 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT) in dispc_vp_set_gamma()
2373 dispc_vp_write_gamma_table(dispc, hw_videoport); in dispc_vp_set_gamma()
2420 static void dispc_k2g_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, in dispc_k2g_vp_write_csc() argument
2433 dispc_vp_write(dispc, hw_videoport, dispc_vp_cpr_coef_reg[i], in dispc_k2g_vp_write_csc()
2437 static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, in dispc_k2g_vp_set_ctm() argument
2446 dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr); in dispc_k2g_vp_set_ctm()
2450 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, in dispc_k2g_vp_set_ctm()
2485 static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, in dispc_k3_vp_write_csc() argument
2499 dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i], in dispc_k3_vp_write_csc()
2503 static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, in dispc_k3_vp_set_ctm() argument
2512 dispc_k3_vp_write_csc(dispc, hw_videoport, &csc); in dispc_k3_vp_set_ctm()
2516 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, in dispc_k3_vp_set_ctm()
2520 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, in dispc_vp_set_color_mgmt() argument
2537 dispc_vp_set_gamma(dispc, hw_videoport, lut, length); in dispc_vp_set_color_mgmt()
2542 if (dispc->feat->subrev == DISPC_K2G) in dispc_vp_set_color_mgmt()
2543 dispc_k2g_vp_set_ctm(dispc, hw_videoport, ctm); in dispc_vp_set_color_mgmt()
2545 dispc_k3_vp_set_ctm(dispc, hw_videoport, ctm); in dispc_vp_set_color_mgmt()
2548 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_setup() argument
2551 dispc_vp_set_default_color(dispc, hw_videoport, 0); in dispc_vp_setup()
2552 dispc_vp_set_color_mgmt(dispc, hw_videoport, state, newmodeset); in dispc_vp_setup()
2555 int dispc_runtime_suspend(struct dispc_device *dispc) in dispc_runtime_suspend() argument
2557 dev_dbg(dispc->dev, "suspend\n"); in dispc_runtime_suspend()
2559 dispc->is_enabled = false; in dispc_runtime_suspend()
2561 clk_disable_unprepare(dispc->fclk); in dispc_runtime_suspend()
2566 int dispc_runtime_resume(struct dispc_device *dispc) in dispc_runtime_resume() argument
2568 dev_dbg(dispc->dev, "resume\n"); in dispc_runtime_resume()
2570 clk_prepare_enable(dispc->fclk); in dispc_runtime_resume()
2572 if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) == 0) in dispc_runtime_resume()
2573 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); in dispc_runtime_resume()
2575 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", in dispc_runtime_resume()
2576 dispc_read(dispc, DSS_REVISION)); in dispc_runtime_resume()
2578 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2579 REG_GET(dispc, DSS_SYSSTATUS, 1, 1), in dispc_runtime_resume()
2580 REG_GET(dispc, DSS_SYSSTATUS, 2, 2), in dispc_runtime_resume()
2581 REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); in dispc_runtime_resume()
2583 if (dispc->feat->subrev == DISPC_AM65X) in dispc_runtime_resume()
2584 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2585 REG_GET(dispc, DSS_SYSSTATUS, 5, 5), in dispc_runtime_resume()
2586 REG_GET(dispc, DSS_SYSSTATUS, 6, 6), in dispc_runtime_resume()
2587 REG_GET(dispc, DSS_SYSSTATUS, 7, 7)); in dispc_runtime_resume()
2589 dev_dbg(dispc->dev, "DISPC IDLE %d\n", in dispc_runtime_resume()
2590 REG_GET(dispc, DSS_SYSSTATUS, 9, 9)); in dispc_runtime_resume()
2592 dispc_initial_config(dispc); in dispc_runtime_resume()
2594 dispc->is_enabled = true; in dispc_runtime_resume()
2596 tidss_irq_resume(dispc->tidss); in dispc_runtime_resume()
2605 tidss->dispc = NULL; in dispc_remove()
2632 struct dispc_device *dispc) in dispc_init_am65x_oldi_io_ctrl() argument
2634 dispc->oldi_io_ctrl = in dispc_init_am65x_oldi_io_ctrl()
2637 if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) { in dispc_init_am65x_oldi_io_ctrl()
2638 dispc->oldi_io_ctrl = NULL; in dispc_init_am65x_oldi_io_ctrl()
2639 } else if (IS_ERR(dispc->oldi_io_ctrl)) { in dispc_init_am65x_oldi_io_ctrl()
2641 __func__, PTR_ERR(dispc->oldi_io_ctrl)); in dispc_init_am65x_oldi_io_ctrl()
2642 return PTR_ERR(dispc->oldi_io_ctrl); in dispc_init_am65x_oldi_io_ctrl()
2647 static void dispc_init_errata(struct dispc_device *dispc) in dispc_init_errata() argument
2655 dispc->errata.i2000 = true; in dispc_init_errata()
2656 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n"); in dispc_init_errata()
2664 struct dispc_device *dispc; in dispc_init() local
2679 dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL); in dispc_init()
2680 if (!dispc) in dispc_init()
2683 dispc->tidss = tidss; in dispc_init()
2684 dispc->dev = dev; in dispc_init()
2685 dispc->feat = feat; in dispc_init()
2687 dispc_init_errata(dispc); in dispc_init()
2689 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats), in dispc_init()
2690 sizeof(*dispc->fourccs), GFP_KERNEL); in dispc_init()
2691 if (!dispc->fourccs) in dispc_init()
2696 if (dispc->errata.i2000 && in dispc_init()
2700 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc; in dispc_init()
2703 dispc->num_fourccs = num_fourccs; in dispc_init()
2705 dispc_common_regmap = dispc->feat->common_regs; in dispc_init()
2707 r = dispc_iomap_resource(pdev, dispc->feat->common, in dispc_init()
2708 &dispc->base_common); in dispc_init()
2712 for (i = 0; i < dispc->feat->num_planes; i++) { in dispc_init()
2713 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i], in dispc_init()
2714 &dispc->base_vid[i]); in dispc_init()
2719 for (i = 0; i < dispc->feat->num_vps; i++) { in dispc_init()
2720 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; in dispc_init()
2724 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i], in dispc_init()
2725 &dispc->base_ovr[i]); in dispc_init()
2729 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i], in dispc_init()
2730 &dispc->base_vp[i]); in dispc_init()
2734 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]); in dispc_init()
2737 dispc->feat->vpclk_name[i], PTR_ERR(clk)); in dispc_init()
2740 dispc->vp_clk[i] = clk; in dispc_init()
2747 dispc->vp_data[i].gamma_table = gamma_table; in dispc_init()
2751 r = dispc_init_am65x_oldi_io_ctrl(dev, dispc); in dispc_init()
2756 dispc->fclk = devm_clk_get(dev, "fck"); in dispc_init()
2757 if (IS_ERR(dispc->fclk)) { in dispc_init()
2759 __func__, PTR_ERR(dispc->fclk)); in dispc_init()
2760 return PTR_ERR(dispc->fclk); in dispc_init()
2762 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk)); in dispc_init()
2764 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", in dispc_init()
2765 &dispc->memory_bandwidth_limit); in dispc_init()
2767 tidss->dispc = dispc; in dispc_init()