Lines Matching +full:gic +full:- +full:v2m +full:- +full:frame
1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
16 #include <linux/dma-iommu.h>
26 #include <linux/irqchip/arm-gic.h>
49 /* APM X-Gene with GICv2m MSI_IIDR register value */
55 /* List of flags for specific v2m implementation */
71 u32 flags; /* v2m flags for specific implementation */
100 static phys_addr_t gicv2m_get_msi_addr(struct v2m_data *v2m, int hwirq) in gicv2m_get_msi_addr() argument
102 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) in gicv2m_get_msi_addr()
103 return v2m->res.start | ((hwirq - 32) << 3); in gicv2m_get_msi_addr()
105 return v2m->res.start + V2M_MSI_SETSPI_NS; in gicv2m_get_msi_addr()
110 struct v2m_data *v2m = irq_data_get_irq_chip_data(data); in gicv2m_compose_msi_msg() local
111 phys_addr_t addr = gicv2m_get_msi_addr(v2m, data->hwirq); in gicv2m_compose_msi_msg()
113 msg->address_hi = upper_32_bits(addr); in gicv2m_compose_msi_msg()
114 msg->address_lo = lower_32_bits(addr); in gicv2m_compose_msi_msg()
116 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) in gicv2m_compose_msi_msg()
117 msg->data = 0; in gicv2m_compose_msi_msg()
119 msg->data = data->hwirq; in gicv2m_compose_msi_msg()
120 if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET) in gicv2m_compose_msi_msg()
121 msg->data -= v2m->spi_offset; in gicv2m_compose_msi_msg()
143 if (is_of_node(domain->parent->fwnode)) { in gicv2m_irq_gic_domain_alloc()
144 fwspec.fwnode = domain->parent->fwnode; in gicv2m_irq_gic_domain_alloc()
147 fwspec.param[1] = hwirq - 32; in gicv2m_irq_gic_domain_alloc()
149 } else if (is_fwnode_irqchip(domain->parent->fwnode)) { in gicv2m_irq_gic_domain_alloc()
150 fwspec.fwnode = domain->parent->fwnode; in gicv2m_irq_gic_domain_alloc()
155 return -EINVAL; in gicv2m_irq_gic_domain_alloc()
163 d = irq_domain_get_irq_data(domain->parent, virq); in gicv2m_irq_gic_domain_alloc()
164 d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING); in gicv2m_irq_gic_domain_alloc()
168 static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq, in gicv2m_unalloc_msi() argument
172 bitmap_release_region(v2m->bm, hwirq - v2m->spi_start, in gicv2m_unalloc_msi()
181 struct v2m_data *v2m = NULL, *tmp; in gicv2m_irq_domain_alloc() local
186 offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis, in gicv2m_irq_domain_alloc()
189 v2m = tmp; in gicv2m_irq_domain_alloc()
195 if (!v2m) in gicv2m_irq_domain_alloc()
196 return -ENOSPC; in gicv2m_irq_domain_alloc()
198 hwirq = v2m->spi_start + offset; in gicv2m_irq_domain_alloc()
200 err = iommu_dma_prepare_msi(info->desc, in gicv2m_irq_domain_alloc()
201 gicv2m_get_msi_addr(v2m, hwirq)); in gicv2m_irq_domain_alloc()
211 &gicv2m_irq_chip, v2m); in gicv2m_irq_domain_alloc()
218 gicv2m_unalloc_msi(v2m, hwirq, nr_irqs); in gicv2m_irq_domain_alloc()
226 struct v2m_data *v2m = irq_data_get_irq_chip_data(d); in gicv2m_irq_domain_free() local
228 gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs); in gicv2m_irq_domain_free()
246 num, V2M_MAX_SPI - V2M_MIN_SPI + 1); in is_msi_spi_valid()
268 struct v2m_data *v2m, *tmp; in gicv2m_teardown() local
270 list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) { in gicv2m_teardown()
271 list_del(&v2m->entry); in gicv2m_teardown()
272 kfree(v2m->bm); in gicv2m_teardown()
273 iounmap(v2m->base); in gicv2m_teardown()
274 of_node_put(to_of_node(v2m->fwnode)); in gicv2m_teardown()
275 if (is_fwnode_irqchip(v2m->fwnode)) in gicv2m_teardown()
276 irq_domain_free_fwnode(v2m->fwnode); in gicv2m_teardown()
277 kfree(v2m); in gicv2m_teardown()
284 struct v2m_data *v2m; in gicv2m_allocate_domains() local
286 v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry); in gicv2m_allocate_domains()
287 if (!v2m) in gicv2m_allocate_domains()
290 inner_domain = irq_domain_create_tree(v2m->fwnode, in gicv2m_allocate_domains()
291 &gicv2m_domain_ops, v2m); in gicv2m_allocate_domains()
294 return -ENOMEM; in gicv2m_allocate_domains()
298 inner_domain->parent = parent; in gicv2m_allocate_domains()
299 pci_domain = pci_msi_create_irq_domain(v2m->fwnode, in gicv2m_allocate_domains()
302 plat_domain = platform_msi_create_irq_domain(v2m->fwnode, in gicv2m_allocate_domains()
312 return -ENOMEM; in gicv2m_allocate_domains()
323 struct v2m_data *v2m; in gicv2m_init_one() local
325 v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL); in gicv2m_init_one()
326 if (!v2m) { in gicv2m_init_one()
328 return -ENOMEM; in gicv2m_init_one()
331 INIT_LIST_HEAD(&v2m->entry); in gicv2m_init_one()
332 v2m->fwnode = fwnode; in gicv2m_init_one()
333 v2m->flags = flags; in gicv2m_init_one()
335 memcpy(&v2m->res, res, sizeof(struct resource)); in gicv2m_init_one()
337 v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res)); in gicv2m_init_one()
338 if (!v2m->base) { in gicv2m_init_one()
340 ret = -ENOMEM; in gicv2m_init_one()
345 v2m->spi_start = spi_start; in gicv2m_init_one()
346 v2m->nr_spis = nr_spis; in gicv2m_init_one()
351 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) { in gicv2m_init_one()
352 ret = -EINVAL; in gicv2m_init_one()
355 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER); in gicv2m_init_one()
357 v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer); in gicv2m_init_one()
358 v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer); in gicv2m_init_one()
361 if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) { in gicv2m_init_one()
362 ret = -EINVAL; in gicv2m_init_one()
367 * APM X-Gene GICv2m implementation has an erratum where in gicv2m_init_one()
375 * is 'spi_number - 32' in gicv2m_init_one()
379 if (!(v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)) { in gicv2m_init_one()
380 switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) { in gicv2m_init_one()
382 v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; in gicv2m_init_one()
383 v2m->spi_offset = v2m->spi_start; in gicv2m_init_one()
386 v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; in gicv2m_init_one()
387 v2m->spi_offset = 32; in gicv2m_init_one()
391 v2m->bm = kcalloc(BITS_TO_LONGS(v2m->nr_spis), sizeof(long), in gicv2m_init_one()
393 if (!v2m->bm) { in gicv2m_init_one()
394 ret = -ENOMEM; in gicv2m_init_one()
398 list_add_tail(&v2m->entry, &v2m_nodes); in gicv2m_init_one()
401 v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1)); in gicv2m_init_one()
405 iounmap(v2m->base); in gicv2m_init_one()
407 kfree(v2m); in gicv2m_init_one()
412 { .compatible = "arm,gic-v2m-frame", },
428 if (!of_find_property(child, "msi-controller", NULL)) in gicv2m_of_init()
433 pr_err("Failed to allocate v2m resource.\n"); in gicv2m_of_init()
437 if (!of_property_read_u32(child, "arm,msi-base-spi", in gicv2m_of_init()
439 !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis)) in gicv2m_of_init()
440 pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n", in gicv2m_of_init()
443 ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, in gicv2m_of_init()
468 /* We only return the fwnode of the first MSI frame. */ in gicv2m_get_fwnode()
473 return data->fwnode; in gicv2m_get_fwnode()
489 rc = !memcmp(madt->header.oem_id, ACPI_AMZN_OEM_ID, ACPI_OEM_ID_SIZE); in acpi_check_amazon_graviton_quirks()
508 return -EINVAL; in acpi_parse_madt_msi()
510 res.start = m->base_address; in acpi_parse_madt_msi()
511 res.end = m->base_address + SZ_4K - 1; in acpi_parse_madt_msi()
516 res.end = res.start + SZ_8K - 1; in acpi_parse_madt_msi()
521 if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) { in acpi_parse_madt_msi()
522 spi_start = m->spi_base; in acpi_parse_madt_msi()
523 nr_spis = m->spi_count; in acpi_parse_madt_msi()
525 pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n", in acpi_parse_madt_msi()
532 return -EINVAL; in acpi_parse_madt_msi()
565 return -EINVAL; in gicv2m_acpi_init()
570 return -EINVAL; in gicv2m_acpi_init()