40 	} while (0)
48 	struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 };  in s5h1432_writereg()
53 		printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, ret == %i)\n",  in s5h1432_writereg()
56 	return (ret != 1) ? -1 : 0;  in s5h1432_writereg()
63 	u8 b1[] = { 0 };  in s5h1432_readreg()
66 		{.addr = addr, .flags = 0, .buf = b0, .len = 1},  in s5h1432_readreg()
75 	return b1[0];  in s5h1432_readreg()
80 	return 0;  in s5h1432_sleep()
88 	u8 reg = 0;  in s5h1432_set_channel_bandwidth()
90 	/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */  in s5h1432_set_channel_bandwidth()
91 	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);  in s5h1432_set_channel_bandwidth()
92 	reg &= ~(0x0C);  in s5h1432_set_channel_bandwidth()
95 		reg |= 0x08;  in s5h1432_set_channel_bandwidth()
98 		reg |= 0x04;  in s5h1432_set_channel_bandwidth()
101 		reg |= 0x00;  in s5h1432_set_channel_bandwidth()
104 		return 0;  in s5h1432_set_channel_bandwidth()
106 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);  in s5h1432_set_channel_bandwidth()
116 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);  in s5h1432_set_IF()
117 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);  in s5h1432_set_IF()
118 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15);  in s5h1432_set_IF()
121 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);  in s5h1432_set_IF()
122 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);  in s5h1432_set_IF()
123 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40);  in s5h1432_set_IF()
126 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);  in s5h1432_set_IF()
127 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);  in s5h1432_set_IF()
128 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0);  in s5h1432_set_IF()
131 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);  in s5h1432_set_IF()
132 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);  in s5h1432_set_IF()
133 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);  in s5h1432_set_IF()
136 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);  in s5h1432_set_IF()
137 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);  in s5h1432_set_IF()
138 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED);  in s5h1432_set_IF()
141 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA);  in s5h1432_set_IF()
142 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA);  in s5h1432_set_IF()
143 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA);  in s5h1432_set_IF()
147 			u32 value = 0;  in s5h1432_set_IF()
151 			       "Default IFFreq %d :reg value = 0x%x\n",  in s5h1432_set_IF()
153 			s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,  in s5h1432_set_IF()
154 					 (u8) value & 0xFF);  in s5h1432_set_IF()
155 			s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5,  in s5h1432_set_IF()
156 					 (u8) (value >> 8) & 0xFF);  in s5h1432_set_IF()
157 			s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7,  in s5h1432_set_IF()
158 					 (u8) (value >> 16) & 0xFF);  in s5h1432_set_IF()
195 			return 0;  in s5h1432_set_frontend()
200 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);  in s5h1432_set_frontend()
202 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);  in s5h1432_set_frontend()
219 			return 0;  in s5h1432_set_frontend()
224 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);  in s5h1432_set_frontend()
226 		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);  in s5h1432_set_frontend()
232 	return 0;  in s5h1432_set_frontend()
239 	u8 reg = 0;  in s5h1432_init()
240 	state->current_frequency = 0;  in s5h1432_init()
246 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);  in s5h1432_init()
247 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);  in s5h1432_init()
248 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);  in s5h1432_init()
249 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);  in s5h1432_init()
250 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);  in s5h1432_init()
251 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);  in s5h1432_init()
252 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);  in s5h1432_init()
253 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);  in s5h1432_init()
254 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);  in s5h1432_init()
255 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);  in s5h1432_init()
256 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);  in s5h1432_init()
257 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);  in s5h1432_init()
258 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);  in s5h1432_init()
259 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);  in s5h1432_init()
260 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);  in s5h1432_init()
261 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);  in s5h1432_init()
262 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);  in s5h1432_init()
263 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);  in s5h1432_init()
264 	/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */  in s5h1432_init()
265 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);  in s5h1432_init()
270 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);  in s5h1432_init()
271 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);  in s5h1432_init()
272 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);  in s5h1432_init()
273 	/* Set reg 0x1E to get the full dynamic range */  in s5h1432_init()
274 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);  in s5h1432_init()
277 	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);  in s5h1432_init()
278 	reg |= 0x80;  in s5h1432_init()
279 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);  in s5h1432_init()
284 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);  in s5h1432_init()
286 	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);  in s5h1432_init()
289 	return 0;  in s5h1432_init()
294 	return 0;  in s5h1432_read_status()
300 	return 0;  in s5h1432_read_signal_strength()
305 	return 0;  in s5h1432_read_snr()
311 	return 0;  in s5h1432_read_ucblocks()
316 	return 0;  in s5h1432_read_ber()
322 	return 0;  in s5h1432_get_tune_settings()