Lines Matching +full:0 +full:x22c
15 .id = 0x00,
19 .id = 0x01,
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
29 .mask = 0xff,
30 .def = 0x4e,
33 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
43 .mask = 0xff,
44 .def = 0x4e,
47 .id = 0x03,
51 .reg = 0x228,
55 .reg = 0x2e8,
57 .mask = 0xff,
58 .def = 0x4e,
61 .id = 0x04,
65 .reg = 0x228,
69 .reg = 0x2f4,
71 .mask = 0xff,
72 .def = 0x4e,
75 .id = 0x05,
79 .reg = 0x228,
83 .reg = 0x2ec,
84 .shift = 0,
85 .mask = 0xff,
86 .def = 0x4e,
89 .id = 0x06,
93 .reg = 0x228,
97 .reg = 0x2f8,
98 .shift = 0,
99 .mask = 0xff,
100 .def = 0x4e,
103 .id = 0x09,
107 .reg = 0x228,
111 .reg = 0x300,
112 .shift = 0,
113 .mask = 0xff,
114 .def = 0x33,
117 .id = 0x0a,
121 .reg = 0x228,
125 .reg = 0x308,
126 .shift = 0,
127 .mask = 0xff,
128 .def = 0x09,
131 .id = 0x0b,
135 .reg = 0x228,
139 .reg = 0x308,
141 .mask = 0xff,
142 .def = 0x09,
145 .id = 0x0f,
149 .reg = 0x228,
153 .reg = 0x2e4,
154 .shift = 0,
155 .mask = 0xff,
156 .def = 0x04,
159 .id = 0x10,
163 .reg = 0x228,
167 .reg = 0x2f0,
168 .shift = 0,
169 .mask = 0xff,
170 .def = 0x68,
173 .id = 0x11,
177 .reg = 0x228,
181 .reg = 0x2fc,
182 .shift = 0,
183 .mask = 0xff,
184 .def = 0x68,
187 .id = 0x12,
191 .reg = 0x228,
195 .reg = 0x334,
196 .shift = 0,
197 .mask = 0xff,
198 .def = 0x0c,
201 .id = 0x13,
205 .reg = 0x228,
209 .reg = 0x33c,
210 .shift = 0,
211 .mask = 0xff,
212 .def = 0x0c,
215 .id = 0x14,
219 .reg = 0x228,
223 .reg = 0x30c,
224 .shift = 0,
225 .mask = 0xff,
226 .def = 0x0a,
229 .id = 0x15,
233 .reg = 0x228,
237 .reg = 0x318,
238 .shift = 0,
239 .mask = 0xff,
240 .def = 0xff,
243 .id = 0x16,
247 .reg = 0x228,
251 .reg = 0x310,
252 .shift = 0,
253 .mask = 0xff,
254 .def = 0x10,
257 .id = 0x17,
261 .reg = 0x228,
265 .reg = 0x310,
267 .mask = 0xff,
268 .def = 0xa5,
271 .id = 0x18,
275 .reg = 0x228,
279 .reg = 0x334,
281 .mask = 0xff,
282 .def = 0x0b,
285 .id = 0x1c,
289 .reg = 0x228,
293 .reg = 0x328,
294 .shift = 0,
295 .mask = 0xff,
296 .def = 0x80,
299 .id = 0x1d,
303 .reg = 0x228,
307 .reg = 0x344,
308 .shift = 0,
309 .mask = 0xff,
310 .def = 0x50,
313 .id = 0x1e,
317 .reg = 0x228,
321 .reg = 0x344,
323 .mask = 0xff,
324 .def = 0xe8,
327 .id = 0x20,
331 .reg = 0x22c,
332 .bit = 0,
335 .reg = 0x338,
336 .shift = 0,
337 .mask = 0xff,
338 .def = 0x0c,
341 .id = 0x22,
345 .reg = 0x22c,
349 .reg = 0x354,
350 .shift = 0,
351 .mask = 0xff,
352 .def = 0xff,
355 .id = 0x23,
359 .reg = 0x22c,
363 .reg = 0x354,
365 .mask = 0xff,
366 .def = 0xff,
369 .id = 0x24,
373 .reg = 0x22c,
377 .reg = 0x358,
378 .shift = 0,
379 .mask = 0xff,
380 .def = 0xb8,
383 .id = 0x25,
387 .reg = 0x22c,
391 .reg = 0x358,
393 .mask = 0xff,
394 .def = 0xee,
397 .id = 0x26,
401 .reg = 0x324,
402 .shift = 0,
403 .mask = 0xff,
404 .def = 0x04,
407 .id = 0x27,
411 .reg = 0x320,
412 .shift = 0,
413 .mask = 0xff,
414 .def = 0x04,
417 .id = 0x28,
421 .reg = 0x22c,
425 .reg = 0x300,
427 .mask = 0xff,
428 .def = 0x33,
431 .id = 0x29,
435 .reg = 0x22c,
439 .reg = 0x304,
440 .shift = 0,
441 .mask = 0xff,
442 .def = 0x6c,
445 .id = 0x2a,
449 .reg = 0x22c,
453 .reg = 0x304,
455 .mask = 0xff,
456 .def = 0x6c,
459 .id = 0x2b,
463 .reg = 0x22c,
467 .reg = 0x328,
469 .mask = 0xff,
470 .def = 0x80,
473 .id = 0x2c,
477 .reg = 0x22c,
481 .reg = 0x364,
482 .shift = 0,
483 .mask = 0xff,
484 .def = 0x47,
487 .id = 0x2d,
491 .reg = 0x22c,
495 .reg = 0x368,
496 .shift = 0,
497 .mask = 0xff,
498 .def = 0xff,
501 .id = 0x2e,
505 .reg = 0x22c,
509 .reg = 0x368,
511 .mask = 0xff,
512 .def = 0xff,
515 .id = 0x2f,
519 .reg = 0x22c,
523 .reg = 0x36c,
524 .shift = 0,
525 .mask = 0xff,
526 .def = 0x47,
529 .id = 0x30,
533 .reg = 0x22c,
537 .reg = 0x30c,
539 .mask = 0xff,
540 .def = 0x9,
543 .id = 0x32,
547 .reg = 0x22c,
551 .reg = 0x2e4,
553 .mask = 0xff,
554 .def = 0x0e,
557 .id = 0x33,
561 .reg = 0x22c,
565 .reg = 0x338,
567 .mask = 0xff,
568 .def = 0x10,
571 .id = 0x34,
575 .reg = 0x22c,
579 .reg = 0x340,
580 .shift = 0,
581 .mask = 0xff,
582 .def = 0x10,
585 .id = 0x35,
589 .reg = 0x22c,
593 .reg = 0x318,
595 .mask = 0xff,
596 .def = 0xff,
599 .id = 0x36,
603 .reg = 0x22c,
607 .reg = 0x314,
608 .shift = 0,
609 .mask = 0xff,
610 .def = 0x25,
613 .id = 0x37,
617 .reg = 0x22c,
621 .reg = 0x31c,
622 .shift = 0,
623 .mask = 0xff,
624 .def = 0xff,
627 .id = 0x38,
631 .reg = 0x324,
633 .mask = 0xff,
634 .def = 0x80,
637 .id = 0x39,
641 .reg = 0x320,
643 .mask = 0xff,
644 .def = 0x0e,
647 .id = 0x3b,
651 .reg = 0x22c,
655 .reg = 0x348,
656 .shift = 0,
657 .mask = 0xff,
658 .def = 0xa5,
661 .id = 0x3c,
665 .reg = 0x22c,
669 .reg = 0x348,
671 .mask = 0xff,
672 .def = 0xe8,
675 .id = 0x3e,
679 .reg = 0x22c,
683 .reg = 0x35c,
684 .shift = 0,
685 .mask = 0xff,
686 .def = 0xff,
689 .id = 0x3f,
693 .reg = 0x22c,
697 .reg = 0x35c,
699 .mask = 0xff,
700 .def = 0xff,
703 .id = 0x40,
707 .reg = 0x230,
708 .bit = 0,
711 .reg = 0x360,
712 .shift = 0,
713 .mask = 0xff,
714 .def = 0x89,
717 .id = 0x41,
721 .reg = 0x230,
725 .reg = 0x360,
727 .mask = 0xff,
728 .def = 0x59,
731 .id = 0x4a,
735 .reg = 0x230,
739 .reg = 0x37c,
740 .shift = 0,
741 .mask = 0xff,
742 .def = 0xa5,
745 .id = 0x4b,
749 .reg = 0x230,
753 .reg = 0x37c,
755 .mask = 0xff,
756 .def = 0xa5,
759 .id = 0x4c,
763 .reg = 0x230,
767 .reg = 0x380,
768 .shift = 0,
769 .mask = 0xff,
770 .def = 0xa5,
773 .id = 0x4d,
777 .reg = 0x230,
781 .reg = 0x380,
783 .mask = 0xff,
784 .def = 0xa5,
787 .id = 0x4e,
791 .reg = 0x230,
795 .reg = 0x388,
796 .shift = 0,
797 .mask = 0xff,
798 .def = 0x10,
801 .id = 0x4f,
805 .reg = 0x230,
809 .reg = 0x384,
810 .shift = 0,
811 .mask = 0xff,
812 .def = 0x0c,
815 .id = 0x50,
819 .reg = 0x230,
823 .reg = 0x388,
825 .mask = 0xff,
826 .def = 0x10,
829 .id = 0x51,
833 .reg = 0x230,
837 .reg = 0x384,
839 .mask = 0xff,
840 .def = 0x0c,
843 .id = 0x52,
847 .reg = 0x38c,
848 .shift = 0,
849 .mask = 0xff,
850 .def = 0x04,
853 .id = 0x53,
857 .reg = 0x38c,
859 .mask = 0xff,
860 .def = 0x0e,
863 .id = 0x54,
867 .reg = 0x230,
871 .reg = 0x390,
872 .shift = 0,
873 .mask = 0xff,
874 .def = 0x50,
877 .id = 0x55,
881 .reg = 0x230,
885 .reg = 0x390,
887 .mask = 0xff,
888 .def = 0x50,
894 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
895 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
896 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
897 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
898 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
899 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
900 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
901 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
902 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
903 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
904 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
905 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
906 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
907 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
908 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
909 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
950 TEGRA114_MC_RESET(AVPC, 0x200, 0x204, 1),
951 TEGRA114_MC_RESET(DC, 0x200, 0x204, 2),
952 TEGRA114_MC_RESET(DCB, 0x200, 0x204, 3),
953 TEGRA114_MC_RESET(EPP, 0x200, 0x204, 4),
954 TEGRA114_MC_RESET(2D, 0x200, 0x204, 5),
955 TEGRA114_MC_RESET(HC, 0x200, 0x204, 6),
956 TEGRA114_MC_RESET(HDA, 0x200, 0x204, 7),
957 TEGRA114_MC_RESET(ISP, 0x200, 0x204, 8),
958 TEGRA114_MC_RESET(MPCORE, 0x200, 0x204, 9),
959 TEGRA114_MC_RESET(MPCORELP, 0x200, 0x204, 10),
960 TEGRA114_MC_RESET(MPE, 0x200, 0x204, 11),
961 TEGRA114_MC_RESET(3D, 0x200, 0x204, 12),
962 TEGRA114_MC_RESET(3D2, 0x200, 0x204, 13),
963 TEGRA114_MC_RESET(PPCS, 0x200, 0x204, 14),
964 TEGRA114_MC_RESET(VDE, 0x200, 0x204, 16),
965 TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
973 .client_id_mask = 0x7f,