Lines Matching +full:0 +full:x100
12 .id = 0x00,
15 .id = 0x01,
18 .id = 0x02,
21 .id = 0x03,
24 .id = 0x04,
27 .id = 0x05,
30 .id = 0x06,
33 .id = 0x07,
36 .id = 0x08,
39 .id = 0x09,
42 .id = 0x0a,
45 .id = 0x0b,
48 .id = 0x0c,
51 .id = 0x0d,
54 .id = 0x0e,
57 .id = 0x0f,
60 .id = 0x10,
63 .id = 0x11,
66 .id = 0x12,
69 .id = 0x13,
72 .id = 0x14,
75 .id = 0x15,
78 .id = 0x16,
81 .id = 0x17,
84 .id = 0x18,
87 .id = 0x19,
90 .id = 0x1a,
93 .id = 0x1b,
96 .id = 0x1c,
99 .id = 0x1d,
102 .id = 0x1e,
105 .id = 0x1f,
108 .id = 0x20,
111 .id = 0x21,
114 .id = 0x22,
117 .id = 0x23,
120 .id = 0x24,
123 .id = 0x25,
126 .id = 0x26,
129 .id = 0x27,
132 .id = 0x28,
135 .id = 0x29,
138 .id = 0x2a,
141 .id = 0x2b,
144 .id = 0x2c,
147 .id = 0x2d,
150 .id = 0x2e,
153 .id = 0x2f,
156 .id = 0x30,
159 .id = 0x31,
162 .id = 0x32,
165 .id = 0x33,
181 TEGRA20_MC_RESET(AVPC, 0x100, 0x140, 0x104, 0),
182 TEGRA20_MC_RESET(DC, 0x100, 0x144, 0x104, 1),
183 TEGRA20_MC_RESET(DCB, 0x100, 0x148, 0x104, 2),
184 TEGRA20_MC_RESET(EPP, 0x100, 0x14c, 0x104, 3),
185 TEGRA20_MC_RESET(2D, 0x100, 0x150, 0x104, 4),
186 TEGRA20_MC_RESET(HC, 0x100, 0x154, 0x104, 5),
187 TEGRA20_MC_RESET(ISP, 0x100, 0x158, 0x104, 6),
188 TEGRA20_MC_RESET(MPCORE, 0x100, 0x15c, 0x104, 7),
189 TEGRA20_MC_RESET(MPEA, 0x100, 0x160, 0x104, 8),
190 TEGRA20_MC_RESET(MPEB, 0x100, 0x164, 0x104, 9),
191 TEGRA20_MC_RESET(MPEC, 0x100, 0x168, 0x104, 10),
192 TEGRA20_MC_RESET(3D, 0x100, 0x16c, 0x104, 11),
193 TEGRA20_MC_RESET(PPCS, 0x100, 0x170, 0x104, 12),
194 TEGRA20_MC_RESET(VDE, 0x100, 0x174, 0x104, 13),
195 TEGRA20_MC_RESET(VI, 0x100, 0x178, 0x104, 14),
211 return 0; in tegra20_mc_hotreset_assert()
227 return 0; in tegra20_mc_hotreset_deassert()
243 return 0; in tegra20_mc_block_dma()
249 return mc_readl(mc, rst->status) == 0; in tegra20_mc_dma_idling()
255 return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0; in tegra20_mc_reset_status()
271 return 0; in tegra20_mc_unblock_dma()
287 .client_id_mask = 0x3f,