25 static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar)  in schedule_cxl_fault()  argument
27 	ctx->dsisr = dsisr;  in schedule_cxl_fault()
35 	u64 dsisr, dar;  in cxl_irq_psl9()  local
37 	dsisr = irq_info->dsisr;  in cxl_irq_psl9()
40 	trace_cxl_psl9_irq(ctx, irq, dsisr, dar);  in cxl_irq_psl9()
42 	pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);  in cxl_irq_psl9()
44 	if (dsisr & CXL_PSL9_DSISR_An_TF) {  in cxl_irq_psl9()
46 		return schedule_cxl_fault(ctx, dsisr, dar);  in cxl_irq_psl9()
49 	if (dsisr & CXL_PSL9_DSISR_An_PE)  in cxl_irq_psl9()
50 		return cxl_ops->handle_psl_slice_error(ctx, dsisr,  in cxl_irq_psl9()
52 	if (dsisr & CXL_PSL9_DSISR_An_AE) {  in cxl_irq_psl9()
77 	if (dsisr & CXL_PSL9_DSISR_An_OC)  in cxl_irq_psl9()
86 	u64 dsisr, dar;  in cxl_irq_psl8()  local
88 	dsisr = irq_info->dsisr;  in cxl_irq_psl8()
91 	trace_cxl_psl_irq(ctx, irq, dsisr, dar);  in cxl_irq_psl8()
93 	pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);  in cxl_irq_psl8()
95 	if (dsisr & CXL_PSL_DSISR_An_DS) {  in cxl_irq_psl8()
107 		return schedule_cxl_fault(ctx, dsisr, dar);  in cxl_irq_psl8()
110 	if (dsisr & CXL_PSL_DSISR_An_M)  in cxl_irq_psl8()
112 	if (dsisr & CXL_PSL_DSISR_An_P)  in cxl_irq_psl8()
114 	if (dsisr & CXL_PSL_DSISR_An_A)  in cxl_irq_psl8()
116 	if (dsisr & CXL_PSL_DSISR_An_S)  in cxl_irq_psl8()
118 	if (dsisr & CXL_PSL_DSISR_An_K)  in cxl_irq_psl8()
121 	if (dsisr & CXL_PSL_DSISR_An_DM) {  in cxl_irq_psl8()
128 		return schedule_cxl_fault(ctx, dsisr, dar);  in cxl_irq_psl8()
130 	if (dsisr & CXL_PSL_DSISR_An_ST)  in cxl_irq_psl8()
132 	if (dsisr & CXL_PSL_DSISR_An_UR)  in cxl_irq_psl8()
134 	if (dsisr & CXL_PSL_DSISR_An_PE)  in cxl_irq_psl8()
135 		return cxl_ops->handle_psl_slice_error(ctx, dsisr,  in cxl_irq_psl8()
137 	if (dsisr & CXL_PSL_DSISR_An_AE) {  in cxl_irq_psl8()
163 	if (dsisr & CXL_PSL_DSISR_An_OC)  in cxl_irq_psl8()