Lines Matching +full:gcc +full:- +full:sm8250
1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
21 #include "sdhci-pltfm.h"
120 #define INVALID_TUNING_PHASE -1
134 /* Max load for eMMC Vdd-io supply */
138 msm_host->var_ops->msm_readl_relaxed(host, offset)
141 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
295 return msm_host->offset; in sdhci_priv_msm_offset()
308 return readl_relaxed(msm_host->core_mem + offset); in sdhci_msm_mci_variant_readl_relaxed()
314 return readl_relaxed(host->ioaddr + offset); in sdhci_msm_v5_variant_readl_relaxed()
323 writel_relaxed(val, msm_host->core_mem + offset); in sdhci_msm_mci_variant_writel_relaxed()
329 writel_relaxed(val, host->ioaddr + offset); in sdhci_msm_v5_variant_writel_relaxed()
335 struct mmc_ios ios = host->mmc->ios; in msm_get_clock_rate_for_bus_mode()
345 host->flags & SDHCI_HS400_TUNING) in msm_get_clock_rate_for_bus_mode()
355 struct mmc_ios curr_ios = host->mmc->ios; in msm_set_clock_rate_for_bus_mode()
356 struct clk *core_clk = msm_host->bulk_clks[0].clk; in msm_set_clock_rate_for_bus_mode()
360 rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), clock); in msm_set_clock_rate_for_bus_mode()
363 mmc_hostname(host->mmc), clock, in msm_set_clock_rate_for_bus_mode()
367 msm_host->clk_rate = clock; in msm_set_clock_rate_for_bus_mode()
369 mmc_hostname(host->mmc), clk_get_rate(core_clk), in msm_set_clock_rate_for_bus_mode()
378 struct mmc_host *mmc = host->mmc; in msm_dll_poll_ck_out_en()
383 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
384 msm_offset->core_dll_config) & CORE_CK_OUT_EN); in msm_dll_poll_ck_out_en()
387 if (--wait_cnt == 0) { in msm_dll_poll_ck_out_en()
390 return -ETIMEDOUT; in msm_dll_poll_ck_out_en()
394 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
395 msm_offset->core_dll_config) & CORE_CK_OUT_EN); in msm_dll_poll_ck_out_en()
410 struct mmc_host *mmc = host->mmc; in msm_config_cm_dll_phase()
415 return -EINVAL; in msm_config_cm_dll_phase()
417 spin_lock_irqsave(&host->lock, flags); in msm_config_cm_dll_phase()
419 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
422 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
433 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
436 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
438 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
440 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
447 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
450 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
457 spin_unlock_irqrestore(&host->lock, flags); in msm_config_cm_dll_phase()
464 * setting for SD3.0 UHS-I card read operation (in SDR104
480 struct mmc_host *mmc = host->mmc; in msm_find_most_appropriate_phase()
485 return -EINVAL; in msm_find_most_appropriate_phase()
503 return -EINVAL; in msm_find_most_appropriate_phase()
505 /* Check if phase-0 is present in first valid window? */ in msm_find_most_appropriate_phase()
536 return -EINVAL; in msm_find_most_appropriate_phase()
560 i--; in msm_find_most_appropriate_phase()
565 ret = -EINVAL; in msm_find_most_appropriate_phase()
580 if (host->clock <= 112000000) in msm_cm_dll_set_freq()
582 else if (host->clock <= 125000000) in msm_cm_dll_set_freq()
584 else if (host->clock <= 137000000) in msm_cm_dll_set_freq()
586 else if (host->clock <= 150000000) in msm_cm_dll_set_freq()
588 else if (host->clock <= 162000000) in msm_cm_dll_set_freq()
590 else if (host->clock <= 175000000) in msm_cm_dll_set_freq()
592 else if (host->clock <= 187000000) in msm_cm_dll_set_freq()
594 else if (host->clock <= 200000000) in msm_cm_dll_set_freq()
597 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
600 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
606 struct mmc_host *mmc = host->mmc; in msm_init_cm_dll()
613 msm_host->offset; in msm_init_cm_dll()
615 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk)) in msm_init_cm_dll()
616 xo_clk = clk_get_rate(msm_host->xo_clk); in msm_init_cm_dll()
618 spin_lock_irqsave(&host->lock, flags); in msm_init_cm_dll()
625 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
627 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
629 if (msm_host->dll_config) in msm_init_cm_dll()
630 writel_relaxed(msm_host->dll_config, in msm_init_cm_dll()
631 host->ioaddr + msm_offset->core_dll_config); in msm_init_cm_dll()
633 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
634 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
635 msm_offset->core_dll_config); in msm_init_cm_dll()
637 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
638 msm_offset->core_dll_config); in msm_init_cm_dll()
640 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
641 msm_offset->core_dll_config_2); in msm_init_cm_dll()
643 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
644 msm_offset->core_dll_config_2); in msm_init_cm_dll()
647 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
648 msm_offset->core_dll_config); in msm_init_cm_dll()
650 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
651 msm_offset->core_dll_config); in msm_init_cm_dll()
653 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
654 msm_offset->core_dll_config); in msm_init_cm_dll()
656 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
657 msm_offset->core_dll_config); in msm_init_cm_dll()
659 if (!msm_host->dll_config) in msm_init_cm_dll()
662 if (msm_host->use_14lpp_dll_reset && in msm_init_cm_dll()
663 !IS_ERR_OR_NULL(msm_host->xo_clk)) { in msm_init_cm_dll()
666 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
667 msm_offset->core_dll_config_2); in msm_init_cm_dll()
670 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), in msm_init_cm_dll()
673 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), in msm_init_cm_dll()
676 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
677 msm_offset->core_dll_config_2); in msm_init_cm_dll()
681 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
682 msm_offset->core_dll_config_2); in msm_init_cm_dll()
687 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
688 msm_offset->core_dll_config); in msm_init_cm_dll()
690 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
691 msm_offset->core_dll_config); in msm_init_cm_dll()
693 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
694 msm_offset->core_dll_config); in msm_init_cm_dll()
696 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
697 msm_offset->core_dll_config); in msm_init_cm_dll()
699 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
700 if (!msm_host->dll_config) in msm_init_cm_dll()
702 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
703 msm_offset->core_dll_config_2); in msm_init_cm_dll()
705 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
706 msm_offset->core_dll_config_2); in msm_init_cm_dll()
713 if (msm_host->uses_tassadar_dll) { in msm_init_cm_dll()
716 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
717 msm_offset->core_dll_usr_ctl); in msm_init_cm_dll()
719 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
720 msm_offset->core_dll_config_3); in msm_init_cm_dll()
722 if (msm_host->clk_rate < 150000000) in msm_init_cm_dll()
726 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
727 msm_offset->core_dll_config_3); in msm_init_cm_dll()
730 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
731 msm_offset->core_dll_config); in msm_init_cm_dll()
733 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
734 msm_offset->core_dll_config); in msm_init_cm_dll()
736 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
737 msm_offset->core_dll_config); in msm_init_cm_dll()
739 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
740 msm_offset->core_dll_config); in msm_init_cm_dll()
743 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) & in msm_init_cm_dll()
746 if (--wait_cnt == 0) { in msm_init_cm_dll()
749 spin_unlock_irqrestore(&host->lock, flags); in msm_init_cm_dll()
750 return -ETIMEDOUT; in msm_init_cm_dll()
755 spin_unlock_irqrestore(&host->lock, flags); in msm_init_cm_dll()
765 msm_host->offset; in msm_hc_select_default()
767 if (!msm_host->use_cdclp533) { in msm_hc_select_default()
768 config = readl_relaxed(host->ioaddr + in msm_hc_select_default()
769 msm_offset->core_vendor_spec3); in msm_hc_select_default()
771 writel_relaxed(config, host->ioaddr + in msm_hc_select_default()
772 msm_offset->core_vendor_spec3); in msm_hc_select_default()
775 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
778 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
787 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
790 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
794 * before changing the clk_rate at GCC. in msm_hc_select_default()
803 struct mmc_ios ios = host->mmc->ios; in msm_hc_select_hs400()
807 msm_host->offset; in msm_hc_select_hs400()
810 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_hs400()
814 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_hs400()
819 if ((msm_host->tuning_done || ios.enhanced_strobe) && in msm_hc_select_hs400()
820 !msm_host->calibration_done) { in msm_hc_select_hs400()
821 config = readl_relaxed(host->ioaddr + in msm_hc_select_hs400()
822 msm_offset->core_vendor_spec); in msm_hc_select_hs400()
825 writel_relaxed(config, host->ioaddr + in msm_hc_select_hs400()
826 msm_offset->core_vendor_spec); in msm_hc_select_hs400()
828 if (!msm_host->clk_rate && !msm_host->use_cdclp533) { in msm_hc_select_hs400()
834 rc = readl_relaxed_poll_timeout(host->ioaddr + in msm_hc_select_hs400()
835 msm_offset->core_dll_status, in msm_hc_select_hs400()
841 if (rc == -ETIMEDOUT) in msm_hc_select_hs400()
843 mmc_hostname(host->mmc), dll_lock); in msm_hc_select_hs400()
847 * before changing the clk_rate at GCC. in msm_hc_select_hs400()
853 * sdhci_msm_hc_select_mode :- In general all timing modes are
858 * HS200 - SDR104 (Since they both are equivalent in functionality)
859 * HS400 - This involves multiple configurations
860 * Initially SDR104 - when tuning is required as HS200
867 * HS400 - divided clock (free running MCLK/2)
868 * All other modes - default (free running MCLK)
872 struct mmc_ios ios = host->mmc->ios; in sdhci_msm_hc_select_mode()
875 host->flags & SDHCI_HS400_TUNING) in sdhci_msm_hc_select_mode()
888 msm_host->offset; in sdhci_msm_cdclp533_calibration()
890 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_cdclp533_calibration()
901 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_cdclp533_calibration()
905 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in sdhci_msm_cdclp533_calibration()
907 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in sdhci_msm_cdclp533_calibration()
909 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
911 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
913 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
915 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
917 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
919 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
921 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
923 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
927 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
928 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); in sdhci_msm_cdclp533_calibration()
929 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
930 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); in sdhci_msm_cdclp533_calibration()
931 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); in sdhci_msm_cdclp533_calibration()
932 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); in sdhci_msm_cdclp533_calibration()
933 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); in sdhci_msm_cdclp533_calibration()
934 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); in sdhci_msm_cdclp533_calibration()
935 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); in sdhci_msm_cdclp533_calibration()
939 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
941 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
943 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
945 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
947 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
949 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
951 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
953 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
955 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, in sdhci_msm_cdclp533_calibration()
960 if (ret == -ETIMEDOUT) { in sdhci_msm_cdclp533_calibration()
962 mmc_hostname(host->mmc), __func__); in sdhci_msm_cdclp533_calibration()
966 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) in sdhci_msm_cdclp533_calibration()
970 mmc_hostname(host->mmc), __func__, ret); in sdhci_msm_cdclp533_calibration()
971 ret = -EINVAL; in sdhci_msm_cdclp533_calibration()
975 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
977 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
979 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_cdclp533_calibration()
986 struct mmc_host *mmc = host->mmc; in sdhci_msm_cm_dll_sdc4_calibration()
994 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_cm_dll_sdc4_calibration()
1003 if (msm_host->updated_ddr_cfg) in sdhci_msm_cm_dll_sdc4_calibration()
1004 ddr_cfg_offset = msm_offset->core_ddr_config; in sdhci_msm_cm_dll_sdc4_calibration()
1006 ddr_cfg_offset = msm_offset->core_ddr_config_old; in sdhci_msm_cm_dll_sdc4_calibration()
1007 writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); in sdhci_msm_cm_dll_sdc4_calibration()
1009 if (mmc->ios.enhanced_strobe) { in sdhci_msm_cm_dll_sdc4_calibration()
1010 config = readl_relaxed(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1011 msm_offset->core_ddr_200_cfg); in sdhci_msm_cm_dll_sdc4_calibration()
1013 writel_relaxed(config, host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1014 msm_offset->core_ddr_200_cfg); in sdhci_msm_cm_dll_sdc4_calibration()
1017 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2); in sdhci_msm_cm_dll_sdc4_calibration()
1019 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2); in sdhci_msm_cm_dll_sdc4_calibration()
1021 ret = readl_relaxed_poll_timeout(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1022 msm_offset->core_dll_status, in sdhci_msm_cm_dll_sdc4_calibration()
1027 if (ret == -ETIMEDOUT) { in sdhci_msm_cm_dll_sdc4_calibration()
1029 mmc_hostname(host->mmc), __func__); in sdhci_msm_cm_dll_sdc4_calibration()
1036 * and MCLK must be switched on for at-least 1us before DATA in sdhci_msm_cm_dll_sdc4_calibration()
1041 if (!msm_host->use_14lpp_dll_reset) { in sdhci_msm_cm_dll_sdc4_calibration()
1042 config = readl_relaxed(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1043 msm_offset->core_vendor_spec3); in sdhci_msm_cm_dll_sdc4_calibration()
1045 writel_relaxed(config, host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1046 msm_offset->core_vendor_spec3); in sdhci_msm_cm_dll_sdc4_calibration()
1055 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_cm_dll_sdc4_calibration()
1064 struct mmc_host *mmc = host->mmc; in sdhci_msm_hs400_dll_calibration()
1068 msm_host->offset; in sdhci_msm_hs400_dll_calibration()
1070 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_hs400_dll_calibration()
1080 if (!mmc->ios.enhanced_strobe) { in sdhci_msm_hs400_dll_calibration()
1083 msm_host->saved_tuning_phase); in sdhci_msm_hs400_dll_calibration()
1086 config = readl_relaxed(host->ioaddr + in sdhci_msm_hs400_dll_calibration()
1087 msm_offset->core_dll_config); in sdhci_msm_hs400_dll_calibration()
1089 writel_relaxed(config, host->ioaddr + in sdhci_msm_hs400_dll_calibration()
1090 msm_offset->core_dll_config); in sdhci_msm_hs400_dll_calibration()
1093 if (msm_host->use_cdclp533) in sdhci_msm_hs400_dll_calibration()
1098 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_hs400_dll_calibration()
1105 struct mmc_ios *ios = &host->mmc->ios; in sdhci_msm_is_tuning_needed()
1111 if (host->clock <= CORE_FREQ_100MHZ || in sdhci_msm_is_tuning_needed()
1112 !(ios->timing == MMC_TIMING_MMC_HS400 || in sdhci_msm_is_tuning_needed()
1113 ios->timing == MMC_TIMING_MMC_HS200 || in sdhci_msm_is_tuning_needed()
1114 ios->timing == MMC_TIMING_UHS_SDR104) || in sdhci_msm_is_tuning_needed()
1115 ios->enhanced_strobe) in sdhci_msm_is_tuning_needed()
1140 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_restore_sdr_dll_config()
1148 u32 config, oldconfig = readl_relaxed(host->ioaddr + in sdhci_msm_set_cdr()
1149 msm_offset->core_dll_config); in sdhci_msm_set_cdr()
1161 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_cdr()
1162 msm_offset->core_dll_config); in sdhci_msm_set_cdr()
1172 struct mmc_ios ios = host->mmc->ios; in sdhci_msm_execute_tuning()
1177 msm_host->use_cdr = false; in sdhci_msm_execute_tuning()
1182 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */ in sdhci_msm_execute_tuning()
1183 msm_host->use_cdr = true; in sdhci_msm_execute_tuning()
1189 msm_host->tuning_done = 0; in sdhci_msm_execute_tuning()
1193 * - select MCLK/2 in VENDOR_SPEC in sdhci_msm_execute_tuning()
1194 * - program MCLK to 400MHz (or nearest supported) in GCC in sdhci_msm_execute_tuning()
1196 if (host->flags & SDHCI_HS400_TUNING) { in sdhci_msm_execute_tuning()
1199 host->flags &= ~SDHCI_HS400_TUNING; in sdhci_msm_execute_tuning()
1235 if (--tuning_seq_cnt) { in sdhci_msm_execute_tuning()
1255 msm_host->saved_tuning_phase = phase; in sdhci_msm_execute_tuning()
1259 if (--tuning_seq_cnt) in sdhci_msm_execute_tuning()
1264 rc = -EIO; in sdhci_msm_execute_tuning()
1268 msm_host->tuning_done = true; in sdhci_msm_execute_tuning()
1273 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1284 if (host->clock > CORE_FREQ_100MHZ && in sdhci_msm_hs400()
1285 (msm_host->tuning_done || ios->enhanced_strobe) && in sdhci_msm_hs400()
1286 !msm_host->calibration_done) { in sdhci_msm_hs400()
1289 msm_host->calibration_done = true; in sdhci_msm_hs400()
1292 mmc_hostname(host->mmc), ret); in sdhci_msm_hs400()
1299 struct mmc_host *mmc = host->mmc; in sdhci_msm_set_uhs_signaling()
1305 msm_host->offset; in sdhci_msm_set_uhs_signaling()
1337 if (host->clock <= CORE_FREQ_100MHZ) { in sdhci_msm_set_uhs_signaling()
1346 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_uhs_signaling()
1347 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1349 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_uhs_signaling()
1350 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1352 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_uhs_signaling()
1353 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1355 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_uhs_signaling()
1356 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1362 msm_host->calibration_done = false; in sdhci_msm_set_uhs_signaling()
1366 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); in sdhci_msm_set_uhs_signaling()
1369 if (mmc->ios.timing == MMC_TIMING_MMC_HS400) in sdhci_msm_set_uhs_signaling()
1370 sdhci_msm_hs400(host, &mmc->ios); in sdhci_msm_set_uhs_signaling()
1375 struct platform_device *pdev = msm_host->pdev; in sdhci_msm_set_pincfg()
1379 ret = pinctrl_pm_select_default_state(&pdev->dev); in sdhci_msm_set_pincfg()
1381 ret = pinctrl_pm_select_sleep_state(&pdev->dev); in sdhci_msm_set_pincfg()
1388 if (IS_ERR(mmc->supply.vmmc)) in sdhci_msm_set_vmmc()
1391 return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd); in sdhci_msm_set_vmmc()
1400 if (msm_host->vqmmc_enabled == level) in msm_toggle_vqmmc()
1405 if (msm_host->caps_0 & CORE_3_0V_SUPPORT) in msm_toggle_vqmmc()
1407 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT) in msm_toggle_vqmmc()
1410 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in msm_toggle_vqmmc()
1418 ret = regulator_enable(mmc->supply.vqmmc); in msm_toggle_vqmmc()
1420 ret = regulator_disable(mmc->supply.vqmmc); in msm_toggle_vqmmc()
1427 msm_host->vqmmc_enabled = level; in msm_toggle_vqmmc()
1438 ret = regulator_set_load(mmc->supply.vqmmc, load); in msm_config_vqmmc_mode()
1451 if (IS_ERR(mmc->supply.vqmmc) || in sdhci_msm_set_vqmmc()
1452 (mmc->ios.power_mode == MMC_POWER_UNDEFINED)) in sdhci_msm_set_vqmmc()
1465 mmc->card && mmc_card_mmc(mmc->card); in sdhci_msm_set_vqmmc()
1477 init_waitqueue_head(&msm_host->pwr_irq_wait); in sdhci_msm_init_pwr_irq_wait()
1483 wake_up(&msm_host->pwr_irq_wait); in sdhci_msm_complete_pwr_irq_wait()
1502 msm_host->offset; in sdhci_msm_check_power_status()
1505 mmc_hostname(host->mmc), __func__, req_type, in sdhci_msm_check_power_status()
1506 msm_host->curr_pwr_state, msm_host->curr_io_level); in sdhci_msm_check_power_status()
1511 * Since sdhci-msm-v5, this bit has been removed and SW must consider in sdhci_msm_check_power_status()
1514 if (!msm_host->mci_removed) in sdhci_msm_check_power_status()
1516 msm_offset->core_generics); in sdhci_msm_check_power_status()
1523 * The IRQ for request type IO High/LOW will be generated when - in sdhci_msm_check_power_status()
1531 * for host->pwr to handle a case where IO voltage high request is in sdhci_msm_check_power_status()
1534 if ((req_type & REQ_IO_HIGH) && !host->pwr) { in sdhci_msm_check_power_status()
1536 mmc_hostname(host->mmc), req_type); in sdhci_msm_check_power_status()
1539 if ((req_type & msm_host->curr_pwr_state) || in sdhci_msm_check_power_status()
1540 (req_type & msm_host->curr_io_level)) in sdhci_msm_check_power_status()
1549 if (!wait_event_timeout(msm_host->pwr_irq_wait, in sdhci_msm_check_power_status()
1550 msm_host->pwr_irq_flag, in sdhci_msm_check_power_status()
1552 dev_warn(&msm_host->pdev->dev, in sdhci_msm_check_power_status()
1554 mmc_hostname(host->mmc), req_type); in sdhci_msm_check_power_status()
1556 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), in sdhci_msm_check_power_status()
1565 msm_host->offset; in sdhci_msm_dump_pwr_ctrl_regs()
1568 mmc_hostname(host->mmc), in sdhci_msm_dump_pwr_ctrl_regs()
1569 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status), in sdhci_msm_dump_pwr_ctrl_regs()
1570 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask), in sdhci_msm_dump_pwr_ctrl_regs()
1571 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl)); in sdhci_msm_dump_pwr_ctrl_regs()
1578 struct mmc_host *mmc = host->mmc; in sdhci_msm_handle_pwr_irq()
1583 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_handle_pwr_irq()
1586 msm_offset->core_pwrctl_status); in sdhci_msm_handle_pwr_irq()
1590 msm_offset->core_pwrctl_clear); in sdhci_msm_handle_pwr_irq()
1600 msm_offset->core_pwrctl_status)) { in sdhci_msm_handle_pwr_irq()
1603 mmc_hostname(host->mmc), irq_status); in sdhci_msm_handle_pwr_irq()
1609 msm_offset->core_pwrctl_clear); in sdhci_msm_handle_pwr_irq()
1610 retry--; in sdhci_msm_handle_pwr_irq()
1648 if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) { in sdhci_msm_handle_pwr_irq()
1649 ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios); in sdhci_msm_handle_pwr_irq()
1653 mmc->ios.signal_voltage, mmc->ios.vdd, in sdhci_msm_handle_pwr_irq()
1665 msm_offset->core_pwrctl_ctl); in sdhci_msm_handle_pwr_irq()
1671 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in sdhci_msm_handle_pwr_irq()
1684 config = readl_relaxed(host->ioaddr + in sdhci_msm_handle_pwr_irq()
1685 msm_offset->core_vendor_spec); in sdhci_msm_handle_pwr_irq()
1689 (msm_host->caps_0 & CORE_3_0V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1692 (msm_host->caps_0 & CORE_1_8V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1696 writel_relaxed(new_config, host->ioaddr + in sdhci_msm_handle_pwr_irq()
1697 msm_offset->core_vendor_spec); in sdhci_msm_handle_pwr_irq()
1701 msm_host->curr_pwr_state = pwr_state; in sdhci_msm_handle_pwr_irq()
1703 msm_host->curr_io_level = io_level; in sdhci_msm_handle_pwr_irq()
1706 mmc_hostname(msm_host->mmc), __func__, irq, irq_status, in sdhci_msm_handle_pwr_irq()
1717 msm_host->pwr_irq_flag = 1; in sdhci_msm_pwr_irq()
1728 struct clk *core_clk = msm_host->bulk_clks[0].clk; in sdhci_msm_get_max_clock()
1739 * __sdhci_msm_set_clock - sdhci_msm clock control.
1743 * instead directly control the GCC clock as per
1750 * Keep actual_clock as zero - in __sdhci_msm_set_clock()
1751 * - since there is no divider used so no need of having actual_clock. in __sdhci_msm_set_clock()
1752 * - MSM controller uses SDCLK for data timeout calculation. If in __sdhci_msm_set_clock()
1753 * actual_clock is zero, host->clock is taken for calculation. in __sdhci_msm_set_clock()
1755 host->mmc->actual_clock = 0; in __sdhci_msm_set_clock()
1771 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1778 msm_host->clk_rate = clock; in sdhci_msm_set_clock()
1803 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_msm_cqe_irq()
1815 * on 16-byte descriptors in 64bit mode. in sdhci_msm_cqe_disable()
1817 if (host->flags & SDHCI_USE_64_BIT_DMA) in sdhci_msm_cqe_disable()
1818 host->desc_sz = 16; in sdhci_msm_cqe_disable()
1820 spin_lock_irqsave(&host->lock, flags); in sdhci_msm_cqe_disable()
1833 spin_unlock_irqrestore(&host->lock, flags); in sdhci_msm_cqe_disable()
1847 * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock. in sdhci_msm_set_timeout()
1849 if (cmd && cmd->data && host->clock > 400000 && in sdhci_msm_set_timeout()
1850 host->clock <= 50000000 && in sdhci_msm_set_timeout()
1851 ((1 << (count + start)) > (10 * host->clock))) in sdhci_msm_set_timeout()
1852 host->data_timeout = 22LL * NSEC_PER_SEC; in sdhci_msm_set_timeout()
1874 if (host->caps & SDHCI_CAN_64BIT) in sdhci_msm_cqe_add_host()
1875 host->alloc_desc_sz = 16; in sdhci_msm_cqe_add_host()
1884 dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret); in sdhci_msm_cqe_add_host()
1888 msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_msm_cqe_add_host()
1889 cq_host->ops = &sdhci_msm_cqhci_ops; in sdhci_msm_cqe_add_host()
1891 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_msm_cqe_add_host()
1893 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_msm_cqe_add_host()
1895 dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n", in sdhci_msm_cqe_add_host()
1896 mmc_hostname(host->mmc), ret); in sdhci_msm_cqe_add_host()
1911 if (host->flags & SDHCI_USE_64_BIT_DMA) in sdhci_msm_cqe_add_host()
1912 host->desc_sz = 12; in sdhci_msm_cqe_add_host()
1918 dev_info(&pdev->dev, "%s: CQE init: success\n", in sdhci_msm_cqe_add_host()
1919 mmc_hostname(host->mmc)); in sdhci_msm_cqe_add_host()
1946 if (host->pwr && (val & SDHCI_RESET_ALL)) in __sdhci_msm_check_write()
1953 msm_host->transfer_mode = val; in __sdhci_msm_check_write()
1956 if (!msm_host->use_cdr) in __sdhci_msm_check_write()
1958 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) && in __sdhci_msm_check_write()
1968 msm_host->pwr_irq_flag = 0; in __sdhci_msm_check_write()
1984 writew_relaxed(val, host->ioaddr + reg); in sdhci_msm_writew()
1997 writeb_relaxed(val, host->ioaddr + reg); in sdhci_msm_writeb()
2005 struct mmc_host *mmc = msm_host->mmc; in sdhci_msm_set_regulator_caps()
2006 struct regulator *supply = mmc->supply.vqmmc; in sdhci_msm_set_regulator_caps()
2009 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_set_regulator_caps()
2011 if (!IS_ERR(mmc->supply.vqmmc)) { in sdhci_msm_set_regulator_caps()
2027 u32 io_level = msm_host->curr_io_level; in sdhci_msm_set_regulator_caps()
2029 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_regulator_caps()
2030 msm_offset->core_vendor_spec); in sdhci_msm_set_regulator_caps()
2039 host->ioaddr + msm_offset->core_vendor_spec); in sdhci_msm_set_regulator_caps()
2041 msm_host->caps_0 |= caps; in sdhci_msm_set_regulator_caps()
2047 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)) in sdhci_msm_reset()
2048 cqhci_deactivate(host->mmc); in sdhci_msm_reset()
2056 ret = mmc_regulator_get_supply(msm_host->mmc); in sdhci_msm_register_vreg()
2075 if (host->version < SDHCI_SPEC_300) in sdhci_msm_start_signal_voltage_switch()
2080 switch (ios->signal_voltage) { in sdhci_msm_start_signal_voltage_switch()
2082 if (!(host->flags & SDHCI_SIGNALING_330)) in sdhci_msm_start_signal_voltage_switch()
2083 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2089 if (!(host->flags & SDHCI_SIGNALING_180)) in sdhci_msm_start_signal_voltage_switch()
2090 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2097 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2114 return -EAGAIN; in sdhci_msm_start_signal_voltage_switch()
2119 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2125 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_dump_vendor_regs()
2127 SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n"); in sdhci_msm_dump_vendor_regs()
2131 readl_relaxed(host->ioaddr + msm_offset->core_dll_status), in sdhci_msm_dump_vendor_regs()
2132 readl_relaxed(host->ioaddr + msm_offset->core_dll_config), in sdhci_msm_dump_vendor_regs()
2133 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2)); in sdhci_msm_dump_vendor_regs()
2136 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3), in sdhci_msm_dump_vendor_regs()
2137 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl), in sdhci_msm_dump_vendor_regs()
2138 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config)); in sdhci_msm_dump_vendor_regs()
2141 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec), in sdhci_msm_dump_vendor_regs()
2142 readl_relaxed(host->ioaddr + in sdhci_msm_dump_vendor_regs()
2143 msm_offset->core_vendor_spec_func2), in sdhci_msm_dump_vendor_regs()
2144 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3)); in sdhci_msm_dump_vendor_regs()
2183 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
2184 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
2185 {.compatible = "qcom,sdm670-sdhci", .data = &sdm845_sdhci_var},
2186 {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
2187 {.compatible = "qcom,sm8250-sdhci", .data = &sm8250_sdhci_var},
2188 {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
2222 struct device_node *node = pdev->dev.of_node; in sdhci_msm_get_of_property()
2226 if (of_property_read_u32(node, "qcom,ddr-config", in sdhci_msm_get_of_property()
2227 &msm_host->ddr_config)) in sdhci_msm_get_of_property()
2228 msm_host->ddr_config = DDR_CONFIG_POR_VAL; in sdhci_msm_get_of_property()
2230 of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config); in sdhci_msm_get_of_property()
2254 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to in sdhci_msm_gcc_reset()
2283 struct device_node *node = pdev->dev.of_node; in sdhci_msm_probe()
2289 host->sdma_boundary = 0; in sdhci_msm_probe()
2292 msm_host->mmc = host->mmc; in sdhci_msm_probe()
2293 msm_host->pdev = pdev; in sdhci_msm_probe()
2295 ret = mmc_of_parse(host->mmc); in sdhci_msm_probe()
2303 var_info = of_device_get_match_data(&pdev->dev); in sdhci_msm_probe()
2305 msm_host->mci_removed = var_info->mci_removed; in sdhci_msm_probe()
2306 msm_host->restore_dll_config = var_info->restore_dll_config; in sdhci_msm_probe()
2307 msm_host->var_ops = var_info->var_ops; in sdhci_msm_probe()
2308 msm_host->offset = var_info->offset; in sdhci_msm_probe()
2309 msm_host->uses_tassadar_dll = var_info->uses_tassadar_dll; in sdhci_msm_probe()
2311 msm_offset = msm_host->offset; in sdhci_msm_probe()
2316 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; in sdhci_msm_probe()
2318 ret = sdhci_msm_gcc_reset(&pdev->dev, host); in sdhci_msm_probe()
2323 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); in sdhci_msm_probe()
2324 if (!IS_ERR(msm_host->bus_clk)) { in sdhci_msm_probe()
2326 ret = clk_set_rate(msm_host->bus_clk, INT_MAX); in sdhci_msm_probe()
2329 ret = clk_prepare_enable(msm_host->bus_clk); in sdhci_msm_probe()
2335 clk = devm_clk_get(&pdev->dev, "iface"); in sdhci_msm_probe()
2338 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); in sdhci_msm_probe()
2341 msm_host->bulk_clks[1].clk = clk; in sdhci_msm_probe()
2344 clk = devm_clk_get(&pdev->dev, "core"); in sdhci_msm_probe()
2347 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); in sdhci_msm_probe()
2350 msm_host->bulk_clks[0].clk = clk; in sdhci_msm_probe()
2353 ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL); in sdhci_msm_probe()
2357 msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core"); in sdhci_msm_probe()
2358 if (IS_ERR(msm_host->opp_table)) { in sdhci_msm_probe()
2359 ret = PTR_ERR(msm_host->opp_table); in sdhci_msm_probe()
2364 ret = dev_pm_opp_of_add_table(&pdev->dev); in sdhci_msm_probe()
2365 if (ret && ret != -ENODEV) { in sdhci_msm_probe()
2366 dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); in sdhci_msm_probe()
2371 ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX); in sdhci_msm_probe()
2373 dev_warn(&pdev->dev, "core clock boost failed\n"); in sdhci_msm_probe()
2375 clk = devm_clk_get(&pdev->dev, "cal"); in sdhci_msm_probe()
2378 msm_host->bulk_clks[2].clk = clk; in sdhci_msm_probe()
2380 clk = devm_clk_get(&pdev->dev, "sleep"); in sdhci_msm_probe()
2383 msm_host->bulk_clks[3].clk = clk; in sdhci_msm_probe()
2385 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
2386 msm_host->bulk_clks); in sdhci_msm_probe()
2394 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); in sdhci_msm_probe()
2395 if (IS_ERR(msm_host->xo_clk)) { in sdhci_msm_probe()
2396 ret = PTR_ERR(msm_host->xo_clk); in sdhci_msm_probe()
2397 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); in sdhci_msm_probe()
2400 if (!msm_host->mci_removed) { in sdhci_msm_probe()
2401 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1); in sdhci_msm_probe()
2402 if (IS_ERR(msm_host->core_mem)) { in sdhci_msm_probe()
2403 ret = PTR_ERR(msm_host->core_mem); in sdhci_msm_probe()
2410 host->ioaddr + msm_offset->core_vendor_spec); in sdhci_msm_probe()
2412 if (!msm_host->mci_removed) { in sdhci_msm_probe()
2415 msm_offset->core_hc_mode); in sdhci_msm_probe()
2417 msm_offset->core_hc_mode); in sdhci_msm_probe()
2420 msm_offset->core_hc_mode); in sdhci_msm_probe()
2423 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); in sdhci_msm_probe()
2424 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", in sdhci_msm_probe()
2429 msm_offset->core_mci_version); in sdhci_msm_probe()
2433 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", in sdhci_msm_probe()
2437 msm_host->use_14lpp_dll_reset = true; in sdhci_msm_probe()
2444 msm_host->use_cdclp533 = true; in sdhci_msm_probe()
2451 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); in sdhci_msm_probe()
2453 writel_relaxed(config, host->ioaddr + in sdhci_msm_probe()
2454 msm_offset->core_vendor_spec_capabilities0); in sdhci_msm_probe()
2458 msm_host->updated_ddr_cfg = true; in sdhci_msm_probe()
2480 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); in sdhci_msm_probe()
2481 if (msm_host->pwr_irq < 0) { in sdhci_msm_probe()
2482 ret = msm_host->pwr_irq; in sdhci_msm_probe()
2489 msm_offset->core_pwrctl_mask); in sdhci_msm_probe()
2491 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, in sdhci_msm_probe()
2493 dev_name(&pdev->dev), host); in sdhci_msm_probe()
2495 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); in sdhci_msm_probe()
2499 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; in sdhci_msm_probe()
2501 pm_runtime_get_noresume(&pdev->dev); in sdhci_msm_probe()
2502 pm_runtime_set_active(&pdev->dev); in sdhci_msm_probe()
2503 pm_runtime_enable(&pdev->dev); in sdhci_msm_probe()
2504 pm_runtime_set_autosuspend_delay(&pdev->dev, in sdhci_msm_probe()
2506 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_msm_probe()
2508 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_msm_probe()
2510 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning; in sdhci_msm_probe()
2511 if (of_property_read_bool(node, "supports-cqe")) in sdhci_msm_probe()
2518 pm_runtime_mark_last_busy(&pdev->dev); in sdhci_msm_probe()
2519 pm_runtime_put_autosuspend(&pdev->dev); in sdhci_msm_probe()
2524 pm_runtime_disable(&pdev->dev); in sdhci_msm_probe()
2525 pm_runtime_set_suspended(&pdev->dev); in sdhci_msm_probe()
2526 pm_runtime_put_noidle(&pdev->dev); in sdhci_msm_probe()
2528 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
2529 msm_host->bulk_clks); in sdhci_msm_probe()
2531 dev_pm_opp_of_remove_table(&pdev->dev); in sdhci_msm_probe()
2533 dev_pm_opp_put_clkname(msm_host->opp_table); in sdhci_msm_probe()
2535 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_probe()
2536 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_probe()
2547 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == in sdhci_msm_remove()
2552 dev_pm_opp_of_remove_table(&pdev->dev); in sdhci_msm_remove()
2553 dev_pm_opp_put_clkname(msm_host->opp_table); in sdhci_msm_remove()
2554 pm_runtime_get_sync(&pdev->dev); in sdhci_msm_remove()
2555 pm_runtime_disable(&pdev->dev); in sdhci_msm_remove()
2556 pm_runtime_put_noidle(&pdev->dev); in sdhci_msm_remove()
2558 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_remove()
2559 msm_host->bulk_clks); in sdhci_msm_remove()
2560 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_remove()
2561 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_remove()
2574 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_suspend()
2575 msm_host->bulk_clks); in sdhci_msm_runtime_suspend()
2587 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_resume()
2588 msm_host->bulk_clks); in sdhci_msm_runtime_resume()
2592 * Whenever core-clock is gated dynamically, it's needed to in sdhci_msm_runtime_resume()
2595 if (msm_host->restore_dll_config && msm_host->clk_rate) in sdhci_msm_runtime_resume()
2598 dev_pm_opp_set_rate(dev, msm_host->clk_rate); in sdhci_msm_runtime_resume()