Lines Matching refs:phyaddr
768 int phyaddr; member
1186 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) in phy_reset()
1195 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_reset()
1220 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) in init_realtek_8211b()
1242 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); in init_realtek_8211c()
1244 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) in init_realtek_8211c()
1246 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1249 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); in init_realtek_8211c()
1252 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) in init_realtek_8211c()
1255 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1267 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201()
1270 if (mii_rw(dev, np->phyaddr, in init_realtek_8201()
1283 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1286 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1290 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1293 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1307 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); in init_cicada()
1310 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) in init_cicada()
1312 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in init_cicada()
1314 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) in init_cicada()
1317 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); in init_cicada()
1319 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) in init_cicada()
1329 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1332 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1335 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1337 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1339 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1343 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1345 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1348 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1351 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1355 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1357 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1359 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1361 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1364 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1367 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1369 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1371 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1375 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1377 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1380 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1396 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in phy_init()
1398 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { in phy_init()
1429 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in phy_init()
1433 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { in phy_init()
1443 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in phy_init()
1446 mii_control_1000 = mii_rw(dev, np->phyaddr, in phy_init()
1454 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { in phy_init()
1462 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1470 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { in phy_init()
1519 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); in phy_init()
1522 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1526 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) in phy_init()
3319 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_force_linkspeed()
3403 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_update_linkspeed()
3416 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3417 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3452 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_update_linkspeed()
3453 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); in nv_update_linkspeed()
3457 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_update_linkspeed()
3458 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); in nv_update_linkspeed()
3525 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ in nv_update_linkspeed()
4383 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_get_link_ksettings()
4393 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_get_link_ksettings()
4405 cmd->base.phy_address = np->phyaddr; in nv_get_link_ksettings()
4429 if (cmd->base.phy_address != np->phyaddr) { in nv_set_link_ksettings()
4488 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4502 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4505 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4509 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4514 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4525 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4532 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4551 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4555 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4557 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4560 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4573 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4634 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_nway_reset()
4644 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_nway_reset()
4840 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_pauseparam()
4846 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_pauseparam()
4850 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_pauseparam()
4852 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_pauseparam()
4881 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_loopback()
4891 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol); in nv_set_loopback()
5035 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5036 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5465 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_open()
5466 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); in nv_open()
5551 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, in nv_open()
5664 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_close()
5665 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); in nv_close()
6050 int phyaddr = i & 0x1F; in nv_probe() local
6053 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); in nv_probe()
6058 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); in nv_probe()
6066 np->phyaddr = phyaddr; in nv_probe()
6074 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; in nv_probe()
6088 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_probe()
6118 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr); in nv_probe()
6167 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); in nv_restore_phy()
6168 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); in nv_restore_phy()
6171 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); in nv_restore_phy()
6172 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); in nv_restore_phy()
6175 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_restore_phy()
6177 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); in nv_restore_phy()