Lines Matching refs:priv
212 struct scc_priv priv[2]; member
221 static void write_scc(struct scc_priv *priv, int reg, int val);
222 static void write_scc_data(struct scc_priv *priv, int val, int fast);
223 static int read_scc(struct scc_priv *priv, int reg);
224 static int read_scc_data(struct scc_priv *priv);
232 static inline void tx_on(struct scc_priv *priv);
233 static inline void rx_on(struct scc_priv *priv);
234 static inline void rx_off(struct scc_priv *priv);
235 static void start_timer(struct scc_priv *priv, int t, int r15);
240 static void rx_isr(struct scc_priv *priv);
241 static void special_condition(struct scc_priv *priv, int rc);
243 static void tx_isr(struct scc_priv *priv);
244 static void es_isr(struct scc_priv *priv);
245 static void tm_isr(struct scc_priv *priv);
280 if (info->priv[0].type == TYPE_TWIN) in dmascc_exit()
282 write_scc(&info->priv[0], R9, FHWRES); in dmascc_exit()
284 hw[info->priv[0].type].io_size); in dmascc_exit()
444 struct scc_priv *priv; in setup_adapter() local
477 priv = &info->priv[0]; in setup_adapter()
478 priv->type = type; in setup_adapter()
479 priv->card_base = card_base; in setup_adapter()
480 priv->scc_cmd = scc_base + SCCA_CMD; in setup_adapter()
481 priv->scc_data = scc_base + SCCA_DATA; in setup_adapter()
482 priv->register_lock = &info->register_lock; in setup_adapter()
485 write_scc(priv, R9, FHWRES | MIE | NV); in setup_adapter()
488 write_scc(priv, R15, SHDLCE); in setup_adapter()
489 if (!read_scc(priv, R15)) { in setup_adapter()
494 write_scc_data(priv, 0, 0); in setup_adapter()
495 if (read_scc(priv, R0) & Tx_BUF_EMP) { in setup_adapter()
503 write_scc(priv, R15, 0); in setup_adapter()
516 write_scc(priv, R15, CTSIE); in setup_adapter()
517 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
518 write_scc(priv, R1, EXT_INT_ENAB); in setup_adapter()
534 write_scc(priv, R1, 0); in setup_adapter()
535 write_scc(priv, R15, 0); in setup_adapter()
536 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
550 priv = &info->priv[i]; in setup_adapter()
551 priv->type = type; in setup_adapter()
552 priv->chip = chip; in setup_adapter()
553 priv->dev = dev; in setup_adapter()
554 priv->info = info; in setup_adapter()
555 priv->channel = i; in setup_adapter()
556 spin_lock_init(&priv->ring_lock); in setup_adapter()
557 priv->register_lock = &info->register_lock; in setup_adapter()
558 priv->card_base = card_base; in setup_adapter()
559 priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD); in setup_adapter()
560 priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA); in setup_adapter()
561 priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1); in setup_adapter()
562 priv->tmr_ctrl = tmr_base + TMR_CTRL; in setup_adapter()
563 priv->tmr_mode = i ? 0xb0 : 0x70; in setup_adapter()
564 priv->param.pclk_hz = hw[type].pclk_hz; in setup_adapter()
565 priv->param.brg_tc = -1; in setup_adapter()
566 priv->param.clocks = TCTRxCP | RCRTxCP; in setup_adapter()
567 priv->param.persist = 256; in setup_adapter()
568 priv->param.dma = -1; in setup_adapter()
569 INIT_WORK(&priv->rx_work, rx_bh); in setup_adapter()
570 dev->ml_priv = priv; in setup_adapter()
600 if (info->priv[0].type == TYPE_TWIN) in setup_adapter()
602 write_scc(&info->priv[0], R9, FHWRES); in setup_adapter()
615 static void write_scc(struct scc_priv *priv, int reg, int val) in write_scc() argument
618 switch (priv->type) { in write_scc()
621 outb(reg, priv->scc_cmd); in write_scc()
622 outb(val, priv->scc_cmd); in write_scc()
626 outb_p(reg, priv->scc_cmd); in write_scc()
627 outb_p(val, priv->scc_cmd); in write_scc()
630 spin_lock_irqsave(priv->register_lock, flags); in write_scc()
631 outb_p(0, priv->card_base + PI_DREQ_MASK); in write_scc()
633 outb_p(reg, priv->scc_cmd); in write_scc()
634 outb_p(val, priv->scc_cmd); in write_scc()
635 outb(1, priv->card_base + PI_DREQ_MASK); in write_scc()
636 spin_unlock_irqrestore(priv->register_lock, flags); in write_scc()
642 static void write_scc_data(struct scc_priv *priv, int val, int fast) in write_scc_data() argument
645 switch (priv->type) { in write_scc_data()
647 outb(val, priv->scc_data); in write_scc_data()
650 outb_p(val, priv->scc_data); in write_scc_data()
654 outb_p(val, priv->scc_data); in write_scc_data()
656 spin_lock_irqsave(priv->register_lock, flags); in write_scc_data()
657 outb_p(0, priv->card_base + PI_DREQ_MASK); in write_scc_data()
658 outb_p(val, priv->scc_data); in write_scc_data()
659 outb(1, priv->card_base + PI_DREQ_MASK); in write_scc_data()
660 spin_unlock_irqrestore(priv->register_lock, flags); in write_scc_data()
667 static int read_scc(struct scc_priv *priv, int reg) in read_scc() argument
671 switch (priv->type) { in read_scc()
674 outb(reg, priv->scc_cmd); in read_scc()
675 return inb(priv->scc_cmd); in read_scc()
678 outb_p(reg, priv->scc_cmd); in read_scc()
679 return inb_p(priv->scc_cmd); in read_scc()
681 spin_lock_irqsave(priv->register_lock, flags); in read_scc()
682 outb_p(0, priv->card_base + PI_DREQ_MASK); in read_scc()
684 outb_p(reg, priv->scc_cmd); in read_scc()
685 rc = inb_p(priv->scc_cmd); in read_scc()
686 outb(1, priv->card_base + PI_DREQ_MASK); in read_scc()
687 spin_unlock_irqrestore(priv->register_lock, flags); in read_scc()
693 static int read_scc_data(struct scc_priv *priv) in read_scc_data() argument
697 switch (priv->type) { in read_scc_data()
699 return inb(priv->scc_data); in read_scc_data()
701 return inb_p(priv->scc_data); in read_scc_data()
703 spin_lock_irqsave(priv->register_lock, flags); in read_scc_data()
704 outb_p(0, priv->card_base + PI_DREQ_MASK); in read_scc_data()
705 rc = inb_p(priv->scc_data); in read_scc_data()
706 outb(1, priv->card_base + PI_DREQ_MASK); in read_scc_data()
707 spin_unlock_irqrestore(priv->register_lock, flags); in read_scc_data()
715 struct scc_priv *priv = dev->ml_priv; in scc_open() local
716 struct scc_info *info = priv->info; in scc_open()
717 int card_base = priv->card_base; in scc_open()
728 if (priv->param.dma >= 0) { in scc_open()
729 if (request_dma(priv->param.dma, "dmascc")) { in scc_open()
735 clear_dma_ff(priv->param.dma); in scc_open()
741 priv->rx_ptr = 0; in scc_open()
742 priv->rx_over = 0; in scc_open()
743 priv->rx_head = priv->rx_tail = priv->rx_count = 0; in scc_open()
744 priv->state = IDLE; in scc_open()
745 priv->tx_head = priv->tx_tail = priv->tx_count = 0; in scc_open()
746 priv->tx_ptr = 0; in scc_open()
749 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_open()
751 write_scc(priv, R4, SDLC | X1CLK); in scc_open()
753 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in scc_open()
755 write_scc(priv, R3, Rx8); in scc_open()
757 write_scc(priv, R5, Tx8); in scc_open()
759 write_scc(priv, R6, 0); in scc_open()
761 write_scc(priv, R7, FLAG); in scc_open()
762 switch (priv->chip) { in scc_open()
765 write_scc(priv, R15, SHDLCE); in scc_open()
767 write_scc(priv, R7, AUTOEOM); in scc_open()
768 write_scc(priv, R15, 0); in scc_open()
772 write_scc(priv, R15, SHDLCE); in scc_open()
792 if (priv->param.dma >= 0) { in scc_open()
793 if (priv->type == TYPE_TWIN) in scc_open()
794 write_scc(priv, R7, AUTOEOM | TXFIFOE); in scc_open()
796 write_scc(priv, R7, AUTOEOM); in scc_open()
798 write_scc(priv, R7, AUTOEOM | RXFIFOH); in scc_open()
800 write_scc(priv, R15, 0); in scc_open()
804 write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ)); in scc_open()
807 if (priv->param.brg_tc >= 0) { in scc_open()
809 write_scc(priv, R12, priv->param.brg_tc & 0xFF); in scc_open()
810 write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF); in scc_open()
813 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL); in scc_open()
815 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL); in scc_open()
818 write_scc(priv, R14, DTRREQ | BRSRC); in scc_open()
822 if (priv->type == TYPE_TWIN) { in scc_open()
825 ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)), in scc_open()
828 write_scc(priv, R11, priv->param.clocks); in scc_open()
829 if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) { in scc_open()
832 (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)), in scc_open()
837 if (priv->type == TYPE_TWIN) { in scc_open()
840 (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)), in scc_open()
845 priv->rr0 = read_scc(priv, R0); in scc_open()
847 write_scc(priv, R15, DCDIE); in scc_open()
857 struct scc_priv *priv = dev->ml_priv; in scc_close() local
858 struct scc_info *info = priv->info; in scc_close()
859 int card_base = priv->card_base; in scc_close()
863 if (priv->type == TYPE_TWIN) { in scc_close()
866 (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)), in scc_close()
871 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_close()
872 if (priv->param.dma >= 0) { in scc_close()
873 if (priv->type == TYPE_TWIN) in scc_close()
875 free_dma(priv->param.dma); in scc_close()
886 struct scc_priv *priv = dev->ml_priv; in scc_ioctl() local
891 (ifr->ifr_data, &priv->param, in scc_ioctl()
901 (&priv->param, ifr->ifr_data, in scc_ioctl()
913 struct scc_priv *priv = dev->ml_priv; in scc_send_packet() local
924 i = priv->tx_head; in scc_send_packet()
925 skb_copy_from_linear_data_offset(skb, 1, priv->tx_buf[i], skb->len - 1); in scc_send_packet()
926 priv->tx_len[i] = skb->len - 1; in scc_send_packet()
930 spin_lock_irqsave(&priv->ring_lock, flags); in scc_send_packet()
932 priv->tx_head = (i + 1) % NUM_TX_BUF; in scc_send_packet()
933 priv->tx_count++; in scc_send_packet()
938 if (priv->tx_count < NUM_TX_BUF) in scc_send_packet()
942 if (priv->state == IDLE) { in scc_send_packet()
944 priv->state = TX_HEAD; in scc_send_packet()
945 priv->tx_start = jiffies; in scc_send_packet()
946 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8); in scc_send_packet()
947 write_scc(priv, R15, 0); in scc_send_packet()
948 start_timer(priv, priv->param.txdelay, 0); in scc_send_packet()
952 spin_unlock_irqrestore(&priv->ring_lock, flags); in scc_send_packet()
967 static inline void tx_on(struct scc_priv *priv) in tx_on() argument
972 if (priv->param.dma >= 0) { in tx_on()
973 n = (priv->chip == Z85230) ? 3 : 1; in tx_on()
976 set_dma_mode(priv->param.dma, DMA_MODE_WRITE); in tx_on()
977 set_dma_addr(priv->param.dma, in tx_on()
978 (int) priv->tx_buf[priv->tx_tail] + n); in tx_on()
979 set_dma_count(priv->param.dma, in tx_on()
980 priv->tx_len[priv->tx_tail] - n); in tx_on()
983 write_scc(priv, R15, TxUIE); in tx_on()
985 if (priv->type == TYPE_TWIN) in tx_on()
986 outb((priv->param.dma == in tx_on()
988 priv->card_base + TWIN_DMA_CFG); in tx_on()
990 write_scc(priv, R1, in tx_on()
994 spin_lock_irqsave(priv->register_lock, flags); in tx_on()
996 write_scc_data(priv, in tx_on()
997 priv->tx_buf[priv->tx_tail][i], 1); in tx_on()
998 enable_dma(priv->param.dma); in tx_on()
999 spin_unlock_irqrestore(priv->register_lock, flags); in tx_on()
1001 write_scc(priv, R15, TxUIE); in tx_on()
1002 write_scc(priv, R1, in tx_on()
1004 tx_isr(priv); in tx_on()
1007 if (priv->chip == Z8530) in tx_on()
1008 write_scc(priv, R0, RES_EOM_L); in tx_on()
1012 static inline void rx_on(struct scc_priv *priv) in rx_on() argument
1017 while (read_scc(priv, R0) & Rx_CH_AV) in rx_on()
1018 read_scc_data(priv); in rx_on()
1019 priv->rx_over = 0; in rx_on()
1020 if (priv->param.dma >= 0) { in rx_on()
1023 set_dma_mode(priv->param.dma, DMA_MODE_READ); in rx_on()
1024 set_dma_addr(priv->param.dma, in rx_on()
1025 (int) priv->rx_buf[priv->rx_head]); in rx_on()
1026 set_dma_count(priv->param.dma, BUF_SIZE); in rx_on()
1028 enable_dma(priv->param.dma); in rx_on()
1030 if (priv->type == TYPE_TWIN) { in rx_on()
1031 outb((priv->param.dma == in rx_on()
1033 priv->card_base + TWIN_DMA_CFG); in rx_on()
1036 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx | in rx_on()
1040 priv->rx_ptr = 0; in rx_on()
1042 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT | in rx_on()
1045 write_scc(priv, R0, ERR_RES); in rx_on()
1046 write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB); in rx_on()
1050 static inline void rx_off(struct scc_priv *priv) in rx_off() argument
1053 write_scc(priv, R3, Rx8); in rx_off()
1055 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN) in rx_off()
1056 outb(0, priv->card_base + TWIN_DMA_CFG); in rx_off()
1058 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in rx_off()
1060 if (priv->param.dma >= 0) in rx_off()
1061 disable_dma(priv->param.dma); in rx_off()
1065 static void start_timer(struct scc_priv *priv, int t, int r15) in start_timer() argument
1067 outb(priv->tmr_mode, priv->tmr_ctrl); in start_timer()
1069 tm_isr(priv); in start_timer()
1071 outb(t & 0xFF, priv->tmr_cnt); in start_timer()
1072 outb((t >> 8) & 0xFF, priv->tmr_cnt); in start_timer()
1073 if (priv->type != TYPE_TWIN) { in start_timer()
1074 write_scc(priv, R15, r15 | CTSIE); in start_timer()
1075 priv->rr0 |= CTS; in start_timer()
1092 while ((is = read_scc(&info->priv[0], R3)) && i--) { in z8530_isr()
1094 rx_isr(&info->priv[0]); in z8530_isr()
1096 tx_isr(&info->priv[0]); in z8530_isr()
1098 es_isr(&info->priv[0]); in z8530_isr()
1100 rx_isr(&info->priv[1]); in z8530_isr()
1102 tx_isr(&info->priv[1]); in z8530_isr()
1104 es_isr(&info->priv[1]); in z8530_isr()
1106 write_scc(&info->priv[0], R0, RES_H_IUS); in z8530_isr()
1122 spin_lock(info->priv[0].register_lock); in scc_isr()
1135 if (info->priv[0].type == TYPE_TWIN) { in scc_isr()
1136 int is, card_base = info->priv[0].card_base; in scc_isr()
1143 tm_isr(&info->priv[0]); in scc_isr()
1146 tm_isr(&info->priv[1]); in scc_isr()
1151 spin_unlock(info->priv[0].register_lock); in scc_isr()
1156 static void rx_isr(struct scc_priv *priv) in rx_isr() argument
1158 if (priv->param.dma >= 0) { in rx_isr()
1160 special_condition(priv, read_scc(priv, R1)); in rx_isr()
1161 write_scc(priv, R0, ERR_RES); in rx_isr()
1166 while (read_scc(priv, R0) & Rx_CH_AV) { in rx_isr()
1167 rc = read_scc(priv, R1); in rx_isr()
1168 if (priv->rx_ptr < BUF_SIZE) in rx_isr()
1169 priv->rx_buf[priv->rx_head][priv-> in rx_isr()
1171 read_scc_data(priv); in rx_isr()
1173 priv->rx_over = 2; in rx_isr()
1174 read_scc_data(priv); in rx_isr()
1176 special_condition(priv, rc); in rx_isr()
1182 static void special_condition(struct scc_priv *priv, int rc) in special_condition() argument
1191 priv->rx_over = 1; in special_condition()
1192 if (priv->param.dma < 0) in special_condition()
1193 write_scc(priv, R0, ERR_RES); in special_condition()
1196 if (priv->param.dma >= 0) { in special_condition()
1198 cb = BUF_SIZE - get_dma_residue(priv->param.dma) - in special_condition()
1202 cb = priv->rx_ptr - 2; in special_condition()
1204 if (priv->rx_over) { in special_condition()
1206 priv->dev->stats.rx_errors++; in special_condition()
1207 if (priv->rx_over == 2) in special_condition()
1208 priv->dev->stats.rx_length_errors++; in special_condition()
1210 priv->dev->stats.rx_fifo_errors++; in special_condition()
1211 priv->rx_over = 0; in special_condition()
1215 priv->dev->stats.rx_errors++; in special_condition()
1216 priv->dev->stats.rx_crc_errors++; in special_condition()
1220 if (priv->rx_count < NUM_RX_BUF - 1) { in special_condition()
1222 priv->rx_len[priv->rx_head] = cb; in special_condition()
1223 priv->rx_head = in special_condition()
1224 (priv->rx_head + in special_condition()
1226 priv->rx_count++; in special_condition()
1227 schedule_work(&priv->rx_work); in special_condition()
1229 priv->dev->stats.rx_errors++; in special_condition()
1230 priv->dev->stats.rx_over_errors++; in special_condition()
1235 if (priv->param.dma >= 0) { in special_condition()
1237 set_dma_addr(priv->param.dma, in special_condition()
1238 (int) priv->rx_buf[priv->rx_head]); in special_condition()
1239 set_dma_count(priv->param.dma, BUF_SIZE); in special_condition()
1242 priv->rx_ptr = 0; in special_condition()
1250 struct scc_priv *priv = container_of(ugli_api, struct scc_priv, rx_work); in rx_bh() local
1251 int i = priv->rx_tail; in rx_bh()
1257 spin_lock_irqsave(&priv->ring_lock, flags); in rx_bh()
1258 while (priv->rx_count) { in rx_bh()
1259 spin_unlock_irqrestore(&priv->ring_lock, flags); in rx_bh()
1260 cb = priv->rx_len[i]; in rx_bh()
1265 priv->dev->stats.rx_dropped++; in rx_bh()
1270 memcpy(&data[1], priv->rx_buf[i], cb); in rx_bh()
1271 skb->protocol = ax25_type_trans(skb, priv->dev); in rx_bh()
1273 priv->dev->stats.rx_packets++; in rx_bh()
1274 priv->dev->stats.rx_bytes += cb; in rx_bh()
1276 spin_lock_irqsave(&priv->ring_lock, flags); in rx_bh()
1278 priv->rx_tail = i = (i + 1) % NUM_RX_BUF; in rx_bh()
1279 priv->rx_count--; in rx_bh()
1281 spin_unlock_irqrestore(&priv->ring_lock, flags); in rx_bh()
1285 static void tx_isr(struct scc_priv *priv) in tx_isr() argument
1287 int i = priv->tx_tail, p = priv->tx_ptr; in tx_isr()
1291 if (p == priv->tx_len[i]) { in tx_isr()
1292 write_scc(priv, R0, RES_Tx_P); in tx_isr()
1297 while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) { in tx_isr()
1298 write_scc_data(priv, priv->tx_buf[i][p++], 0); in tx_isr()
1302 if (!priv->tx_ptr && p && priv->chip == Z8530) in tx_isr()
1303 write_scc(priv, R0, RES_EOM_L); in tx_isr()
1305 priv->tx_ptr = p; in tx_isr()
1309 static void es_isr(struct scc_priv *priv) in es_isr() argument
1315 rr0 = read_scc(priv, R0); in es_isr()
1316 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1317 drr0 = priv->rr0 ^ rr0; in es_isr()
1318 priv->rr0 = rr0; in es_isr()
1322 if (priv->state == TX_DATA) { in es_isr()
1324 i = priv->tx_tail; in es_isr()
1325 if (priv->param.dma >= 0) { in es_isr()
1326 disable_dma(priv->param.dma); in es_isr()
1328 res = get_dma_residue(priv->param.dma); in es_isr()
1331 res = priv->tx_len[i] - priv->tx_ptr; in es_isr()
1332 priv->tx_ptr = 0; in es_isr()
1335 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN) in es_isr()
1336 outb(0, priv->card_base + TWIN_DMA_CFG); in es_isr()
1338 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in es_isr()
1341 priv->dev->stats.tx_errors++; in es_isr()
1342 priv->dev->stats.tx_fifo_errors++; in es_isr()
1344 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1345 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1348 priv->dev->stats.tx_packets++; in es_isr()
1349 priv->dev->stats.tx_bytes += priv->tx_len[i]; in es_isr()
1351 priv->tx_tail = (i + 1) % NUM_TX_BUF; in es_isr()
1352 priv->tx_count--; in es_isr()
1354 netif_wake_queue(priv->dev); in es_isr()
1357 write_scc(priv, R15, 0); in es_isr()
1358 if (priv->tx_count && in es_isr()
1359 (jiffies - priv->tx_start) < priv->param.txtimeout) { in es_isr()
1360 priv->state = TX_PAUSE; in es_isr()
1361 start_timer(priv, priv->param.txpause, 0); in es_isr()
1363 priv->state = TX_TAIL; in es_isr()
1364 start_timer(priv, priv->param.txtail, 0); in es_isr()
1371 switch (priv->state) { in es_isr()
1374 priv->state = DCD_ON; in es_isr()
1375 write_scc(priv, R15, 0); in es_isr()
1376 start_timer(priv, priv->param.dcdon, 0); in es_isr()
1379 switch (priv->state) { in es_isr()
1381 rx_off(priv); in es_isr()
1382 priv->state = DCD_OFF; in es_isr()
1383 write_scc(priv, R15, 0); in es_isr()
1384 start_timer(priv, priv->param.dcdoff, 0); in es_isr()
1390 if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN) in es_isr()
1391 tm_isr(priv); in es_isr()
1396 static void tm_isr(struct scc_priv *priv) in tm_isr() argument
1398 switch (priv->state) { in tm_isr()
1401 tx_on(priv); in tm_isr()
1402 priv->state = TX_DATA; in tm_isr()
1405 write_scc(priv, R5, TxCRC_ENAB | Tx8); in tm_isr()
1406 priv->state = RTS_OFF; in tm_isr()
1407 if (priv->type != TYPE_TWIN) in tm_isr()
1408 write_scc(priv, R15, 0); in tm_isr()
1409 start_timer(priv, priv->param.rtsoff, 0); in tm_isr()
1412 write_scc(priv, R15, DCDIE); in tm_isr()
1413 priv->rr0 = read_scc(priv, R0); in tm_isr()
1414 if (priv->rr0 & DCD) { in tm_isr()
1415 priv->dev->stats.collisions++; in tm_isr()
1416 rx_on(priv); in tm_isr()
1417 priv->state = RX_ON; in tm_isr()
1419 priv->state = WAIT; in tm_isr()
1420 start_timer(priv, priv->param.waittime, DCDIE); in tm_isr()
1424 if (priv->tx_count) { in tm_isr()
1425 priv->state = TX_HEAD; in tm_isr()
1426 priv->tx_start = jiffies; in tm_isr()
1427 write_scc(priv, R5, in tm_isr()
1429 write_scc(priv, R15, 0); in tm_isr()
1430 start_timer(priv, priv->param.txdelay, 0); in tm_isr()
1432 priv->state = IDLE; in tm_isr()
1433 if (priv->type != TYPE_TWIN) in tm_isr()
1434 write_scc(priv, R15, DCDIE); in tm_isr()
1439 write_scc(priv, R15, DCDIE); in tm_isr()
1440 priv->rr0 = read_scc(priv, R0); in tm_isr()
1441 if (priv->rr0 & DCD) { in tm_isr()
1442 rx_on(priv); in tm_isr()
1443 priv->state = RX_ON; in tm_isr()
1445 priv->state = WAIT; in tm_isr()
1446 start_timer(priv, in tm_isr()
1447 random() / priv->param.persist * in tm_isr()
1448 priv->param.slottime, DCDIE); in tm_isr()