33 		  SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)  in ath9k_hw_set_txq_interrupts()
34 		  | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));  in ath9k_hw_set_txq_interrupts()
36 		  SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)  in ath9k_hw_set_txq_interrupts()
37 		  | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));  in ath9k_hw_set_txq_interrupts()
124 			  (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));  in ath9k_hw_updatetxtriglevel()
391 		  SM(cwMin, AR_D_LCL_IFS_CWMIN) |  in ath9k_hw_resettxqueue()
392 		  SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |  in ath9k_hw_resettxqueue()
393 		  SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));  in ath9k_hw_resettxqueue()
396 		  SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |  in ath9k_hw_resettxqueue()
397 		  SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |  in ath9k_hw_resettxqueue()
398 		  SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));  in ath9k_hw_resettxqueue()
411 			  SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |  in ath9k_hw_resettxqueue()
412 			  SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));  in ath9k_hw_resettxqueue()
419 			  SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |  in ath9k_hw_resettxqueue()
424 		  SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |  in ath9k_hw_resettxqueue()
463 			REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)  in ath9k_hw_resettxqueue()
464 				  | SM(0, AR_D_LCL_IFS_CWMAX)  in ath9k_hw_resettxqueue()
465 				  | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));  in ath9k_hw_resettxqueue()
499 			    SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,  in ath9k_hw_resettxqueue()
1037 		filter = SM(set, AR_D_TXBLK_WRITE_COMMAND);  in ath9k_hw_set_tx_filter()
1038 		filter |= SM(dcu_idx, AR_D_TXBLK_WRITE_DCU);  in ath9k_hw_set_tx_filter()
1039 		filter |= SM((destidx / ATH9K_HW_SLICE_PER_DCU),  in ath9k_hw_set_tx_filter()