Lines Matching refs:pcie
299 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
301 writel(val, pcie->base + reg); in advk_writel()
304 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
306 return readl(pcie->base + reg); in advk_readl()
309 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
314 val = advk_readl(pcie, CFG_REG); in advk_pcie_ltssm_state()
319 static inline bool advk_pcie_link_up(struct advk_pcie *pcie) in advk_pcie_link_up() argument
322 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_up()
326 static inline bool advk_pcie_link_active(struct advk_pcie *pcie) in advk_pcie_link_active() argument
336 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_active()
340 static inline bool advk_pcie_link_training(struct advk_pcie *pcie) in advk_pcie_link_training() argument
347 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_training()
354 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) in advk_pcie_wait_for_link() argument
360 if (advk_pcie_link_up(pcie)) in advk_pcie_wait_for_link()
369 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) in advk_pcie_wait_for_retrain() argument
374 if (advk_pcie_link_training(pcie)) in advk_pcie_wait_for_retrain()
380 static void advk_pcie_issue_perst(struct advk_pcie *pcie) in advk_pcie_issue_perst() argument
382 if (!pcie->reset_gpio) in advk_pcie_issue_perst()
386 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); in advk_pcie_issue_perst()
387 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_issue_perst()
389 gpiod_set_value_cansleep(pcie->reset_gpio, 0); in advk_pcie_issue_perst()
392 static void advk_pcie_train_link(struct advk_pcie *pcie) in advk_pcie_train_link() argument
394 struct device *dev = &pcie->pdev->dev; in advk_pcie_train_link()
402 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
404 if (pcie->link_gen == 3) in advk_pcie_train_link()
406 else if (pcie->link_gen == 2) in advk_pcie_train_link()
410 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
417 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
419 if (pcie->link_gen == 3) in advk_pcie_train_link()
421 else if (pcie->link_gen == 2) in advk_pcie_train_link()
425 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
428 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
430 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
436 advk_pcie_issue_perst(pcie); in advk_pcie_train_link()
449 ret = advk_pcie_wait_for_link(pcie); in advk_pcie_train_link()
460 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, in advk_pcie_set_ob_win() argument
464 advk_writel(pcie, OB_WIN_ENABLE | in advk_pcie_set_ob_win()
466 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); in advk_pcie_set_ob_win()
467 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); in advk_pcie_set_ob_win()
468 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); in advk_pcie_set_ob_win()
469 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); in advk_pcie_set_ob_win()
470 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); in advk_pcie_set_ob_win()
471 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); in advk_pcie_set_ob_win()
474 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) in advk_pcie_disable_ob_win() argument
476 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); in advk_pcie_disable_ob_win()
477 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); in advk_pcie_disable_ob_win()
478 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); in advk_pcie_disable_ob_win()
479 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); in advk_pcie_disable_ob_win()
480 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); in advk_pcie_disable_ob_win()
481 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); in advk_pcie_disable_ob_win()
482 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); in advk_pcie_disable_ob_win()
485 static void advk_pcie_setup_hw(struct advk_pcie *pcie) in advk_pcie_setup_hw() argument
496 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
499 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
502 reg = advk_readl(pcie, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
505 advk_writel(pcie, reg, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
508 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
510 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
520 advk_writel(pcie, reg, VENDOR_ID_REG); in advk_pcie_setup_hw()
537 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
540 advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
543 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
545 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
552 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); in advk_pcie_setup_hw()
555 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
562 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
567 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
570 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
573 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
576 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
578 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
581 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); in advk_pcie_setup_hw()
582 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); in advk_pcie_setup_hw()
583 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); in advk_pcie_setup_hw()
584 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); in advk_pcie_setup_hw()
589 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
591 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); in advk_pcie_setup_hw()
594 advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); in advk_pcie_setup_hw()
598 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); in advk_pcie_setup_hw()
610 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
612 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
619 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); in advk_pcie_setup_hw()
627 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_setup_hw()
629 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_setup_hw()
636 for (i = 0; i < pcie->wins_count; i++) in advk_pcie_setup_hw()
637 advk_pcie_set_ob_win(pcie, i, in advk_pcie_setup_hw()
638 pcie->wins[i].match, pcie->wins[i].remap, in advk_pcie_setup_hw()
639 pcie->wins[i].mask, pcie->wins[i].actions); in advk_pcie_setup_hw()
642 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) in advk_pcie_setup_hw()
643 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_setup_hw()
645 advk_pcie_train_link(pcie); in advk_pcie_setup_hw()
648 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) in advk_pcie_check_pio_status() argument
650 struct device *dev = &pcie->pdev->dev; in advk_pcie_check_pio_status()
656 reg = advk_readl(pcie, PIO_STAT); in advk_pcie_check_pio_status()
684 *val = advk_readl(pcie, PIO_RD_DATA); in advk_pcie_check_pio_status()
750 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); in advk_pcie_check_pio_status()
755 static int advk_pcie_wait_pio(struct advk_pcie *pcie) in advk_pcie_wait_pio() argument
757 struct device *dev = &pcie->pdev->dev; in advk_pcie_wait_pio()
763 start = advk_readl(pcie, PIO_START); in advk_pcie_wait_pio()
764 isr = advk_readl(pcie, PIO_ISR); in advk_pcie_wait_pio()
778 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_read() local
782 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_read()
793 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) in advk_pci_bridge_emul_base_conf_read()
810 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_write() local
814 advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_write()
819 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
824 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
837 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_read() local
846 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_pcie_conf_read()
854 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG); in advk_pci_bridge_emul_pcie_conf_read()
855 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG); in advk_pci_bridge_emul_pcie_conf_read()
863 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
876 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & in advk_pci_bridge_emul_pcie_conf_read()
878 if (advk_pcie_link_training(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
880 if (advk_pcie_link_active(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
888 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
900 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_write() local
904 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
908 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
910 advk_pcie_wait_for_retrain(pcie); in advk_pci_bridge_emul_pcie_conf_write()
915 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) & in advk_pci_bridge_emul_pcie_conf_write()
919 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_pcie_conf_write()
925 advk_writel(pcie, new, PCIE_ISR0_REG); in advk_pci_bridge_emul_pcie_conf_write()
944 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) in advk_sw_pci_bridge_init() argument
946 struct pci_bridge_emul *bridge = &pcie->bridge; in advk_sw_pci_bridge_init()
949 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); in advk_sw_pci_bridge_init()
951 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); in advk_sw_pci_bridge_init()
953 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); in advk_sw_pci_bridge_init()
973 bridge->data = pcie; in advk_sw_pci_bridge_init()
979 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, in advk_pcie_valid_device() argument
989 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) in advk_pcie_valid_device()
995 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie) in advk_pcie_pio_is_running() argument
997 struct device *dev = &pcie->pdev->dev; in advk_pcie_pio_is_running()
1016 if (advk_readl(pcie, PIO_START)) { in advk_pcie_pio_is_running()
1027 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_rd_conf() local
1033 if (!advk_pcie_valid_device(pcie, bus, devfn)) { in advk_pcie_rd_conf()
1039 return pci_bridge_emul_conf_read(&pcie->bridge, where, in advk_pcie_rd_conf()
1048 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & in advk_pcie_rd_conf()
1051 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_rd_conf()
1055 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_rd_conf()
1061 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_rd_conf()
1065 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_rd_conf()
1066 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_rd_conf()
1069 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); in advk_pcie_rd_conf()
1074 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_rd_conf()
1075 advk_writel(pcie, 1, PIO_START); in advk_pcie_rd_conf()
1077 ret = advk_pcie_wait_pio(pcie); in advk_pcie_rd_conf()
1084 ret = advk_pcie_check_pio_status(pcie, allow_crs, val); in advk_pcie_rd_conf()
1115 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_wr_conf() local
1122 if (!advk_pcie_valid_device(pcie, bus, devfn)) in advk_pcie_wr_conf()
1126 return pci_bridge_emul_conf_write(&pcie->bridge, where, in advk_pcie_wr_conf()
1132 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_wr_conf()
1136 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_wr_conf()
1142 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_wr_conf()
1146 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_wr_conf()
1147 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_wr_conf()
1155 advk_writel(pcie, reg, PIO_WR_DATA); in advk_pcie_wr_conf()
1158 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); in advk_pcie_wr_conf()
1163 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_wr_conf()
1164 advk_writel(pcie, 1, PIO_START); in advk_pcie_wr_conf()
1166 ret = advk_pcie_wait_pio(pcie); in advk_pcie_wr_conf()
1172 ret = advk_pcie_check_pio_status(pcie, false, NULL); in advk_pcie_wr_conf()
1186 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); in advk_msi_irq_compose_msi_msg() local
1187 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); in advk_msi_irq_compose_msi_msg()
1204 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_alloc() local
1207 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1208 hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM, in advk_msi_irq_domain_alloc()
1210 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1216 &pcie->msi_bottom_irq_chip, in advk_msi_irq_domain_alloc()
1227 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_free() local
1229 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1230 bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs)); in advk_msi_irq_domain_free()
1231 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1241 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_mask() local
1246 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1247 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1249 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1250 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1255 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_unmask() local
1260 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1261 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1263 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1264 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1270 struct advk_pcie *pcie = h->host_data; in advk_pcie_irq_map() local
1274 irq_set_chip_and_handler(virq, &pcie->irq_chip, in advk_pcie_irq_map()
1276 irq_set_chip_data(virq, pcie); in advk_pcie_irq_map()
1286 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_msi_irq_domain() argument
1288 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_msi_irq_domain()
1294 mutex_init(&pcie->msi_used_lock); in advk_pcie_init_msi_irq_domain()
1296 bottom_ic = &pcie->msi_bottom_irq_chip; in advk_pcie_init_msi_irq_domain()
1302 msi_ic = &pcie->msi_irq_chip; in advk_pcie_init_msi_irq_domain()
1305 msi_di = &pcie->msi_domain_info; in advk_pcie_init_msi_irq_domain()
1310 msi_msg_phys = virt_to_phys(&pcie->msi_msg); in advk_pcie_init_msi_irq_domain()
1312 advk_writel(pcie, lower_32_bits(msi_msg_phys), in advk_pcie_init_msi_irq_domain()
1314 advk_writel(pcie, upper_32_bits(msi_msg_phys), in advk_pcie_init_msi_irq_domain()
1317 pcie->msi_inner_domain = in advk_pcie_init_msi_irq_domain()
1319 &advk_msi_domain_ops, pcie); in advk_pcie_init_msi_irq_domain()
1320 if (!pcie->msi_inner_domain) in advk_pcie_init_msi_irq_domain()
1323 pcie->msi_domain = in advk_pcie_init_msi_irq_domain()
1325 msi_di, pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1326 if (!pcie->msi_domain) { in advk_pcie_init_msi_irq_domain()
1327 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1334 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_msi_irq_domain() argument
1336 irq_domain_remove(pcie->msi_domain); in advk_pcie_remove_msi_irq_domain()
1337 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_remove_msi_irq_domain()
1340 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_irq_domain() argument
1342 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_irq_domain()
1348 raw_spin_lock_init(&pcie->irq_lock); in advk_pcie_init_irq_domain()
1356 irq_chip = &pcie->irq_chip; in advk_pcie_init_irq_domain()
1369 pcie->irq_domain = in advk_pcie_init_irq_domain()
1371 &advk_pcie_irq_domain_ops, pcie); in advk_pcie_init_irq_domain()
1372 if (!pcie->irq_domain) { in advk_pcie_init_irq_domain()
1383 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_irq_domain() argument
1385 irq_domain_remove(pcie->irq_domain); in advk_pcie_remove_irq_domain()
1388 static void advk_pcie_handle_msi(struct advk_pcie *pcie) in advk_pcie_handle_msi() argument
1393 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_pcie_handle_msi()
1394 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1401 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1402 virq = irq_find_mapping(pcie->msi_inner_domain, msi_idx); in advk_pcie_handle_msi()
1406 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, in advk_pcie_handle_msi()
1410 static void advk_pcie_handle_int(struct advk_pcie *pcie) in advk_pcie_handle_int() argument
1416 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); in advk_pcie_handle_int()
1417 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_handle_int()
1420 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); in advk_pcie_handle_int()
1421 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_handle_int()
1426 advk_pcie_handle_msi(pcie); in advk_pcie_handle_int()
1433 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), in advk_pcie_handle_int()
1436 virq = irq_find_mapping(pcie->irq_domain, i); in advk_pcie_handle_int()
1443 struct advk_pcie *pcie = arg; in advk_pcie_irq_handler() local
1446 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1450 advk_pcie_handle_int(pcie); in advk_pcie_irq_handler()
1453 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1458 static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) in advk_pcie_disable_phy() argument
1460 phy_power_off(pcie->phy); in advk_pcie_disable_phy()
1461 phy_exit(pcie->phy); in advk_pcie_disable_phy()
1464 static int advk_pcie_enable_phy(struct advk_pcie *pcie) in advk_pcie_enable_phy() argument
1468 if (!pcie->phy) in advk_pcie_enable_phy()
1471 ret = phy_init(pcie->phy); in advk_pcie_enable_phy()
1475 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); in advk_pcie_enable_phy()
1477 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1481 ret = phy_power_on(pcie->phy); in advk_pcie_enable_phy()
1483 dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n"); in advk_pcie_enable_phy()
1485 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1492 static int advk_pcie_setup_phy(struct advk_pcie *pcie) in advk_pcie_setup_phy() argument
1494 struct device *dev = &pcie->pdev->dev; in advk_pcie_setup_phy()
1498 pcie->phy = devm_of_phy_get(dev, node, NULL); in advk_pcie_setup_phy()
1499 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) in advk_pcie_setup_phy()
1500 return PTR_ERR(pcie->phy); in advk_pcie_setup_phy()
1503 if (IS_ERR(pcie->phy)) { in advk_pcie_setup_phy()
1504 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); in advk_pcie_setup_phy()
1505 pcie->phy = NULL; in advk_pcie_setup_phy()
1509 ret = advk_pcie_enable_phy(pcie); in advk_pcie_setup_phy()
1519 struct advk_pcie *pcie; in advk_pcie_probe() local
1528 pcie = pci_host_bridge_priv(bridge); in advk_pcie_probe()
1529 pcie->pdev = pdev; in advk_pcie_probe()
1530 platform_set_drvdata(pdev, pcie); in advk_pcie_probe()
1566 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { in advk_pcie_probe()
1576 pcie->wins_count, (unsigned long long)start, in advk_pcie_probe()
1580 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; in advk_pcie_probe()
1581 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); in advk_pcie_probe()
1583 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; in advk_pcie_probe()
1584 pcie->wins[pcie->wins_count].match = start; in advk_pcie_probe()
1586 pcie->wins[pcie->wins_count].remap = start - entry->offset; in advk_pcie_probe()
1587 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); in advk_pcie_probe()
1589 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) in advk_pcie_probe()
1594 pcie->wins_count++; in advk_pcie_probe()
1598 dev_err(&pcie->pdev->dev, in advk_pcie_probe()
1606 pcie->base = devm_platform_ioremap_resource(pdev, 0); in advk_pcie_probe()
1607 if (IS_ERR(pcie->base)) in advk_pcie_probe()
1608 return PTR_ERR(pcie->base); in advk_pcie_probe()
1616 pcie); in advk_pcie_probe()
1622 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, in advk_pcie_probe()
1626 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); in advk_pcie_probe()
1629 pcie->reset_gpio = NULL; in advk_pcie_probe()
1640 pcie->link_gen = 3; in advk_pcie_probe()
1642 pcie->link_gen = ret; in advk_pcie_probe()
1644 ret = advk_pcie_setup_phy(pcie); in advk_pcie_probe()
1648 advk_pcie_setup_hw(pcie); in advk_pcie_probe()
1650 ret = advk_sw_pci_bridge_init(pcie); in advk_pcie_probe()
1656 ret = advk_pcie_init_irq_domain(pcie); in advk_pcie_probe()
1662 ret = advk_pcie_init_msi_irq_domain(pcie); in advk_pcie_probe()
1665 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1669 bridge->sysdata = pcie; in advk_pcie_probe()
1674 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_probe()
1675 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1684 struct advk_pcie *pcie = platform_get_drvdata(pdev); in advk_pcie_remove() local
1685 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in advk_pcie_remove()
1693 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_remove()
1694 advk_pcie_remove_irq_domain(pcie); in advk_pcie_remove()
1698 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_remove()