Lines Matching defs:dst
94 #define REGSPEC_CFG_I_TX_WORDMODE0_SET(dst, src) \ argument
96 #define REGSPEC_CFG_I_RX_WORDMODE0_SET(dst, src) \ argument
99 #define REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(dst, src) \ argument
102 #define CFG_I_SPD_SEL_CDR_OVR1_SET(dst, src) \ argument
109 #define CFG_IND_ADDR_SET(dst, src) \ argument
114 #define I_RESET_B_SET(dst, src) \ argument
116 #define I_PLL_FBDIV_SET(dst, src) \ argument
118 #define I_CUSTOMEROV_SET(dst, src) \ argument
126 #define CMU_REG0_PLL_REF_SEL_SET(dst, src) \ argument
129 #define CMU_REG0_CAL_COUNT_RESOL_SET(dst, src) \ argument
132 #define CMU_REG1_PLL_CP_SET(dst, src) \ argument
134 #define CMU_REG1_PLL_MANUALCAL_SET(dst, src) \ argument
136 #define CMU_REG1_PLL_CP_SEL_SET(dst, src) \ argument
139 #define CMU_REG1_REFCLK_CMOS_SEL_SET(dst, src) \ argument
142 #define CMU_REG2_PLL_REFDIV_SET(dst, src) \ argument
144 #define CMU_REG2_PLL_LFRES_SET(dst, src) \ argument
146 #define CMU_REG2_PLL_FBDIV_SET(dst, src) \ argument
149 #define CMU_REG3_VCOVARSEL_SET(dst, src) \ argument
151 #define CMU_REG3_VCO_MOMSEL_INIT_SET(dst, src) \ argument
153 #define CMU_REG3_VCO_MANMOMSEL_SET(dst, src) \ argument
157 #define CMU_REG5_PLL_LFSMCAP_SET(dst, src) \ argument
159 #define CMU_REG5_PLL_LOCK_RESOLUTION_SET(dst, src) \ argument
161 #define CMU_REG5_PLL_LFCAP_SET(dst, src) \ argument
165 #define CMU_REG6_PLL_VREGTRIM_SET(dst, src) \ argument
167 #define CMU_REG6_MAN_PVT_CAL_SET(dst, src) \ argument
182 #define CMU_REG9_TX_WORD_MODE_CH1_SET(dst, src) \ argument
184 #define CMU_REG9_TX_WORD_MODE_CH0_SET(dst, src) \ argument
186 #define CMU_REG9_PLL_POST_DIVBY2_SET(dst, src) \ argument
188 #define CMU_REG9_VBG_BYPASSB_SET(dst, src) \ argument
190 #define CMU_REG9_IGEN_BYPASS_SET(dst, src) \ argument
193 #define CMU_REG10_VREG_REFSEL_SET(dst, src) \ argument
197 #define CMU_REG12_STATE_DELAY9_SET(dst, src) \ argument
205 #define CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(dst, src) \ argument
207 #define CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(dst, src) \ argument
209 #define CMU_REG16_BYPASS_PLL_LOCK_SET(dst, src) \ argument
212 #define CMU_REG17_PVT_CODE_R2A_SET(dst, src) \ argument
214 #define CMU_REG17_RESERVED_7_SET(dst, src) \ argument
226 #define CMU_REG26_FORCE_PLL_LOCK_SET(dst, src) \ argument
232 #define CMU_REG30_LOCK_COUNT_SET(dst, src) \ argument
234 #define CMU_REG30_PCIE_MODE_SET(dst, src) \ argument
239 #define CMU_REG32_PVT_CAL_WAIT_SEL_SET(dst, src) \ argument
241 #define CMU_REG32_IREF_ADJ_SET(dst, src) \ argument
245 #define CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(dst, src) \ argument
247 #define CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(dst, src) \ argument
249 #define CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(dst, src) \ argument
251 #define CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(dst, src) \ argument
254 #define CMU_REG35_PLL_SSC_MOD_SET(dst, src) \ argument
257 #define CMU_REG36_PLL_SSC_EN_SET(dst, src) \ argument
259 #define CMU_REG36_PLL_SSC_VSTEP_SET(dst, src) \ argument
261 #define CMU_REG36_PLL_SSC_DSMSEL_SET(dst, src) \ argument
269 #define RXTX_REG0_CTLE_EQ_HR_SET(dst, src) \ argument
271 #define RXTX_REG0_CTLE_EQ_QR_SET(dst, src) \ argument
273 #define RXTX_REG0_CTLE_EQ_FR_SET(dst, src) \ argument
276 #define RXTX_REG1_RXACVCM_SET(dst, src) \ argument
278 #define RXTX_REG1_CTLE_EQ_SET(dst, src) \ argument
280 #define RXTX_REG1_RXVREG1_SET(dst, src) \ argument
282 #define RXTX_REG1_RXIREF_ADJ_SET(dst, src) \ argument
285 #define RXTX_REG2_VTT_ENA_SET(dst, src) \ argument
287 #define RXTX_REG2_TX_FIFO_ENA_SET(dst, src) \ argument
289 #define RXTX_REG2_VTT_SEL_SET(dst, src) \ argument
293 #define RXTX_REG4_TX_DATA_RATE_SET(dst, src) \ argument
295 #define RXTX_REG4_TX_WORD_MODE_SET(dst, src) \ argument
298 #define RXTX_REG5_TX_CN1_SET(dst, src) \ argument
300 #define RXTX_REG5_TX_CP1_SET(dst, src) \ argument
302 #define RXTX_REG5_TX_CN2_SET(dst, src) \ argument
305 #define RXTX_REG6_TXAMP_CNTL_SET(dst, src) \ argument
307 #define RXTX_REG6_TXAMP_ENA_SET(dst, src) \ argument
309 #define RXTX_REG6_RX_BIST_ERRCNT_RD_SET(dst, src) \ argument
311 #define RXTX_REG6_TX_IDLE_SET(dst, src) \ argument
313 #define RXTX_REG6_RX_BIST_RESYNC_SET(dst, src) \ argument
318 #define RXTX_REG7_BIST_ENA_RX_SET(dst, src) \ argument
320 #define RXTX_REG7_RX_WORD_MODE_SET(dst, src) \ argument
323 #define RXTX_REG8_CDR_LOOP_ENA_SET(dst, src) \ argument
325 #define RXTX_REG8_CDR_BYPASS_RXLOS_SET(dst, src) \ argument
327 #define RXTX_REG8_SSC_ENABLE_SET(dst, src) \ argument
329 #define RXTX_REG8_SD_VREF_SET(dst, src) \ argument
331 #define RXTX_REG8_SD_DISABLE_SET(dst, src) \ argument
334 #define RXTX_REG7_RESETB_RXD_SET(dst, src) \ argument
336 #define RXTX_REG7_RESETB_RXA_SET(dst, src) \ argument
339 #define RXTX_REG7_LOOP_BACK_ENA_CTLE_SET(dst, src) \ argument
342 #define RXTX_REG11_PHASE_ADJUST_LIMIT_SET(dst, src) \ argument
345 #define RXTX_REG12_LATCH_OFF_ENA_SET(dst, src) \ argument
347 #define RXTX_REG12_SUMOS_ENABLE_SET(dst, src) \ argument
350 #define RXTX_REG12_RX_DET_TERM_ENABLE_SET(dst, src) \ argument
354 #define RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(dst, src) \ argument
356 #define RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(dst, src) \ argument
359 #define RXTX_REG26_PERIOD_ERROR_LATCH_SET(dst, src) \ argument
361 #define RXTX_REG26_BLWC_ENA_SET(dst, src) \ argument
381 #define RXTX_REG38_CUSTOMER_PINMODE_INV_SET(dst, src) \ argument
401 #define RXTX_REG61_ISCAN_INBERT_SET(dst, src) \ argument
403 #define RXTX_REG61_LOADFREQ_SHIFT_SET(dst, src) \ argument
405 #define RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(dst, src) \ argument
407 #define RXTX_REG61_SPD_SEL_CDR_SET(dst, src) \ argument
410 #define RXTX_REG62_PERIOD_H1_QLATCH_SET(dst, src) \ argument
413 #define RXTX_REG89_MU_TH7_SET(dst, src) \ argument
415 #define RXTX_REG89_MU_TH8_SET(dst, src) \ argument
417 #define RXTX_REG89_MU_TH9_SET(dst, src) \ argument
420 #define RXTX_REG96_MU_FREQ1_SET(dst, src) \ argument
422 #define RXTX_REG96_MU_FREQ2_SET(dst, src) \ argument
424 #define RXTX_REG96_MU_FREQ3_SET(dst, src) \ argument
427 #define RXTX_REG99_MU_PHASE1_SET(dst, src) \ argument
429 #define RXTX_REG99_MU_PHASE2_SET(dst, src) \ argument
431 #define RXTX_REG99_MU_PHASE3_SET(dst, src) \ argument
434 #define RXTX_REG102_FREQLOOP_LIMIT_SET(dst, src) \ argument
440 #define RXTX_REG125_PQ_REG_SET(dst, src) \ argument
442 #define RXTX_REG125_SIGN_PQ_SET(dst, src) \ argument
444 #define RXTX_REG125_SIGN_PQ_2C_SET(dst, src) \ argument
446 #define RXTX_REG125_PHZ_MANUALCODE_SET(dst, src) \ argument
448 #define RXTX_REG125_PHZ_MANUAL_SET(dst, src) \ argument
453 #define RXTX_REG127_FORCE_SUM_CAL_START_SET(dst, src) \ argument
455 #define RXTX_REG127_FORCE_LAT_CAL_START_SET(dst, src) \ argument
457 #define RXTX_REG127_LATCH_MAN_CAL_ENA_SET(dst, src) \ argument
459 #define RXTX_REG127_DO_LATCH_MANCAL_SET(dst, src) \ argument
461 #define RXTX_REG127_XO_LATCH_MANCAL_SET(dst, src) \ argument
464 #define RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(dst, src) \ argument
466 #define RXTX_REG128_EO_LATCH_MANCAL_SET(dst, src) \ argument
468 #define RXTX_REG128_SO_LATCH_MANCAL_SET(dst, src) \ argument
471 #define RXTX_REG129_DE_LATCH_MANCAL_SET(dst, src) \ argument
473 #define RXTX_REG129_XE_LATCH_MANCAL_SET(dst, src) \ argument
476 #define RXTX_REG130_EE_LATCH_MANCAL_SET(dst, src) \ argument
478 #define RXTX_REG130_SE_LATCH_MANCAL_SET(dst, src) \ argument
481 #define RXTX_REG145_TX_IDLE_SATA_SET(dst, src) \ argument
483 #define RXTX_REG145_RXES_ENA_SET(dst, src) \ argument
485 #define RXTX_REG145_RXDFE_CONFIG_SET(dst, src) \ argument
487 #define RXTX_REG145_RXVWES_LATENA_SET(dst, src) \ argument