Lines Matching +full:0 +full:x650
21 #define AM33XX_GMII_SEL_MODE_MII 0
26 PHY_GMII_SEL_PORT_MODE = 0,
64 int ret, rgmii_id = 0; in phy_gmii_sel_mode()
65 u32 gmii_sel_mode = 0; in phy_gmii_sel_mode()
125 return 0; in phy_gmii_sel_mode()
131 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 0, 1),
132 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 4, 4),
133 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 6, 6),
136 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 2, 3),
137 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 5, 5),
138 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 7, 7),
153 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 0, 1),
156 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 4, 5),
175 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), },
176 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), },
177 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), },
178 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), },
179 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), },
180 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), },
181 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), },
182 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), },
225 int phy_id = args->args[0]; in phy_gmii_sel_of_xlate()
308 return 0; in phy_gmii_init_phy()
322 offset = of_get_address(dev->of_node, 0, &size, NULL); in phy_gmii_sel_init_ports()
337 for (i = 0; i < priv->num_ports; i++) { in phy_gmii_sel_init_ports()
344 return 0; in phy_gmii_sel_init_ports()
389 return 0; in phy_gmii_sel_probe()