Lines Matching +full:pinctrl +full:- +full:0
15 * a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm.
18 * gpio_a (8 - 11)
19 * +----------
21 * gpio_a (8-11) | gpio_b (0 - 3)
22 * ------------------------+-------+----------
24 * | pwm (0 - 3)
25 * +----------
31 #include <linux/pinctrl/pinconf.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/pinctrl/pinctrl.h>
34 #include <linux/pinctrl/pinmux.h>
39 #include "../pinctrl-utils.h"
41 #define NSP_MUX_BASE0 0x00
42 #define NSP_MUX_BASE1 0x01
43 #define NSP_MUX_BASE2 0x02
47 * @base: base 0 or base 1
100 * nsp IOMUX pinctrl core
152 NSP_PIN_DESC(0, "spi_clk", 1),
170 NSP_PIN_DESC(18, "synce", 0),
171 NSP_PIN_DESC(19, "sata0_led", 0),
172 NSP_PIN_DESC(20, "sata1_led", 0),
178 NSP_PIN_DESC(26, "p5_led0", 0),
179 NSP_PIN_DESC(27, "p5_led1", 0),
184 NSP_PIN_DESC(32, "nand_ale", 0),
185 NSP_PIN_DESC(33, "nand_ce0", 0),
186 NSP_PIN_DESC(34, "nand_r/b", 0),
187 NSP_PIN_DESC(35, "nand_dq0", 0),
188 NSP_PIN_DESC(36, "nand_dq1", 0),
189 NSP_PIN_DESC(37, "nand_dq2", 0),
190 NSP_PIN_DESC(38, "nand_dq3", 0),
191 NSP_PIN_DESC(39, "nand_dq4", 0),
192 NSP_PIN_DESC(40, "nand_dq5", 0),
193 NSP_PIN_DESC(41, "nand_dq6", 0),
194 NSP_PIN_DESC(42, "nand_dq7", 0),
201 static const unsigned int spi_pins[] = {0, 1, 2, 3};
244 NSP_PIN_GROUP(spi, NSP_MUX_BASE0, 0, 0x0f, 0x00),
245 NSP_PIN_GROUP(i2c, NSP_MUX_BASE0, 3, 0x03, 0x00),
246 NSP_PIN_GROUP(mdio, NSP_MUX_BASE0, 5, 0x03, 0x00),
247 NSP_PIN_GROUP(gpio_b_0, NSP_MUX_BASE0, 7, 0x01, 0x00),
248 NSP_PIN_GROUP(pwm0, NSP_MUX_BASE1, 0, 0x01, 0x01),
249 NSP_PIN_GROUP(gpio_b_1, NSP_MUX_BASE0, 8, 0x01, 0x00),
250 NSP_PIN_GROUP(pwm1, NSP_MUX_BASE1, 1, 0x01, 0x01),
251 NSP_PIN_GROUP(gpio_b_2, NSP_MUX_BASE0, 9, 0x01, 0x00),
252 NSP_PIN_GROUP(pwm2, NSP_MUX_BASE1, 2, 0x01, 0x01),
253 NSP_PIN_GROUP(gpio_b_3, NSP_MUX_BASE0, 10, 0x01, 0x00),
254 NSP_PIN_GROUP(pwm3, NSP_MUX_BASE1, 3, 0x01, 0x01),
255 NSP_PIN_GROUP(uart1, NSP_MUX_BASE0, 11, 0x0f, 0x00),
256 NSP_PIN_GROUP(uart2, NSP_MUX_BASE0, 15, 0x03, 0x00),
257 NSP_PIN_GROUP(synce, NSP_MUX_BASE0, 17, 0x01, 0x01),
258 NSP_PIN_GROUP(sata0_led, NSP_MUX_BASE0, 18, 0x01, 0x01),
259 NSP_PIN_GROUP(sata1_led, NSP_MUX_BASE0, 19, 0x01, 0x01),
260 NSP_PIN_GROUP(xtal_out, NSP_MUX_BASE0, 20, 0x01, 0x00),
261 NSP_PIN_GROUP(sdio_pwr, NSP_MUX_BASE0, 21, 0x01, 0x00),
262 NSP_PIN_GROUP(sdio_1p8v, NSP_MUX_BASE0, 22, 0x01, 0x00),
263 NSP_PIN_GROUP(switch_p05_led0, NSP_MUX_BASE0, 26, 0x01, 0x01),
264 NSP_PIN_GROUP(switch_p05_led1, NSP_MUX_BASE0, 27, 0x01, 0x01),
265 NSP_PIN_GROUP(nand, NSP_MUX_BASE2, 0, 0x01, 0x00),
266 NSP_PIN_GROUP(emmc, NSP_MUX_BASE2, 0, 0x01, 0x01)
320 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in nsp_get_groups_count() local
322 return pinctrl->num_groups; in nsp_get_groups_count()
328 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in nsp_get_group_name() local
330 return pinctrl->groups[selector].name; in nsp_get_group_name()
337 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in nsp_get_group_pins() local
339 *pins = pinctrl->groups[selector].pins; in nsp_get_group_pins()
340 *num_pins = pinctrl->groups[selector].num_pins; in nsp_get_group_pins()
342 return 0; in nsp_get_group_pins()
348 seq_printf(s, " %s", dev_name(pctrl_dev->dev)); in nsp_pin_dbg_show()
362 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in nsp_get_functions_count() local
364 return pinctrl->num_functions; in nsp_get_functions_count()
370 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in nsp_get_function_name() local
372 return pinctrl->functions[selector].name; in nsp_get_function_name()
380 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in nsp_get_function_groups() local
382 *groups = pinctrl->functions[selector].groups; in nsp_get_function_groups()
383 *num_groups = pinctrl->functions[selector].num_groups; in nsp_get_function_groups()
385 return 0; in nsp_get_function_groups()
388 static int nsp_pinmux_set(struct nsp_pinctrl *pinctrl, in nsp_pinmux_set() argument
393 const struct nsp_mux *mux = &grp->mux; in nsp_pinmux_set()
399 for (i = 0; i < pinctrl->num_groups; i++) { in nsp_pinmux_set()
400 if ((mux->shift != mux_log[i].mux.shift) || in nsp_pinmux_set()
401 (mux->base != mux_log[i].mux.base)) in nsp_pinmux_set()
412 if (mux_log[i].mux.alt != mux->alt) { in nsp_pinmux_set()
413 dev_err(pinctrl->dev, in nsp_pinmux_set()
415 dev_err(pinctrl->dev, "func:%s grp:%s\n", in nsp_pinmux_set()
416 func->name, grp->name); in nsp_pinmux_set()
417 return -EINVAL; in nsp_pinmux_set()
420 return 0; in nsp_pinmux_set()
422 if (i == pinctrl->num_groups) in nsp_pinmux_set()
423 return -EINVAL; in nsp_pinmux_set()
425 mask = mux->mask; in nsp_pinmux_set()
426 mux_log[i].mux.alt = mux->alt; in nsp_pinmux_set()
429 switch (mux->base) { in nsp_pinmux_set()
431 base_address = pinctrl->base0; in nsp_pinmux_set()
435 base_address = pinctrl->base1; in nsp_pinmux_set()
439 base_address = pinctrl->base2; in nsp_pinmux_set()
443 return -EINVAL; in nsp_pinmux_set()
446 spin_lock_irqsave(&pinctrl->lock, flags); in nsp_pinmux_set()
448 val &= ~(mask << grp->mux.shift); in nsp_pinmux_set()
449 val |= grp->mux.alt << grp->mux.shift; in nsp_pinmux_set()
451 spin_unlock_irqrestore(&pinctrl->lock, flags); in nsp_pinmux_set()
453 return 0; in nsp_pinmux_set()
459 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in nsp_pinmux_enable() local
463 if (grp_select >= pinctrl->num_groups || in nsp_pinmux_enable()
464 func_select >= pinctrl->num_functions) in nsp_pinmux_enable()
465 return -EINVAL; in nsp_pinmux_enable()
467 func = &pinctrl->functions[func_select]; in nsp_pinmux_enable()
468 grp = &pinctrl->groups[grp_select]; in nsp_pinmux_enable()
470 dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n", in nsp_pinmux_enable()
471 func_select, func->name, grp_select, grp->name); in nsp_pinmux_enable()
473 dev_dbg(pctrl_dev->dev, "shift:%u alt:%u\n", grp->mux.shift, in nsp_pinmux_enable()
474 grp->mux.alt); in nsp_pinmux_enable()
476 return nsp_pinmux_set(pinctrl, func, grp, pinctrl->mux_log); in nsp_pinmux_enable()
484 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in nsp_gpio_request_enable() local
485 u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data; in nsp_gpio_request_enable()
489 spin_lock_irqsave(&pinctrl->lock, flags); in nsp_gpio_request_enable()
490 val = readl(pinctrl->base0); in nsp_gpio_request_enable()
494 writel(val, pinctrl->base0); in nsp_gpio_request_enable()
496 spin_unlock_irqrestore(&pinctrl->lock, flags); in nsp_gpio_request_enable()
498 return 0; in nsp_gpio_request_enable()
505 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in nsp_gpio_disable_free() local
506 u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data; in nsp_gpio_disable_free()
510 spin_lock_irqsave(&pinctrl->lock, flags); in nsp_gpio_disable_free()
511 val = readl(pinctrl->base0); in nsp_gpio_disable_free()
516 writel(val, pinctrl->base0); in nsp_gpio_disable_free()
518 spin_unlock_irqrestore(&pinctrl->lock, flags); in nsp_gpio_disable_free()
531 .name = "nsp-pinmux",
536 static int nsp_mux_log_init(struct nsp_pinctrl *pinctrl) in nsp_mux_log_init() argument
542 pinctrl->mux_log = devm_kcalloc(pinctrl->dev, no_of_groups, in nsp_mux_log_init()
545 if (!pinctrl->mux_log) in nsp_mux_log_init()
546 return -ENOMEM; in nsp_mux_log_init()
548 for (i = 0; i < no_of_groups; i++) { in nsp_mux_log_init()
549 log = &pinctrl->mux_log[i]; in nsp_mux_log_init()
550 log->mux.base = nsp_pin_groups[i].mux.base; in nsp_mux_log_init()
551 log->mux.shift = nsp_pin_groups[i].mux.shift; in nsp_mux_log_init()
552 log->mux.alt = 0; in nsp_mux_log_init()
553 log->is_configured = false; in nsp_mux_log_init()
556 return 0; in nsp_mux_log_init()
561 struct nsp_pinctrl *pinctrl; in nsp_pinmux_probe() local
567 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL); in nsp_pinmux_probe()
568 if (!pinctrl) in nsp_pinmux_probe()
569 return -ENOMEM; in nsp_pinmux_probe()
570 pinctrl->dev = &pdev->dev; in nsp_pinmux_probe()
571 platform_set_drvdata(pdev, pinctrl); in nsp_pinmux_probe()
572 spin_lock_init(&pinctrl->lock); in nsp_pinmux_probe()
574 pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0); in nsp_pinmux_probe()
575 if (IS_ERR(pinctrl->base0)) in nsp_pinmux_probe()
576 return PTR_ERR(pinctrl->base0); in nsp_pinmux_probe()
580 return -EINVAL; in nsp_pinmux_probe()
581 pinctrl->base1 = devm_ioremap(&pdev->dev, res->start, in nsp_pinmux_probe()
583 if (!pinctrl->base1) { in nsp_pinmux_probe()
584 dev_err(&pdev->dev, "unable to map I/O space\n"); in nsp_pinmux_probe()
585 return -ENOMEM; in nsp_pinmux_probe()
588 pinctrl->base2 = devm_platform_ioremap_resource(pdev, 2); in nsp_pinmux_probe()
589 if (IS_ERR(pinctrl->base2)) in nsp_pinmux_probe()
590 return PTR_ERR(pinctrl->base2); in nsp_pinmux_probe()
592 ret = nsp_mux_log_init(pinctrl); in nsp_pinmux_probe()
594 dev_err(&pdev->dev, "unable to initialize IOMUX log\n"); in nsp_pinmux_probe()
598 pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL); in nsp_pinmux_probe()
600 return -ENOMEM; in nsp_pinmux_probe()
602 for (i = 0; i < num_pins; i++) { in nsp_pinmux_probe()
608 pinctrl->groups = nsp_pin_groups; in nsp_pinmux_probe()
609 pinctrl->num_groups = ARRAY_SIZE(nsp_pin_groups); in nsp_pinmux_probe()
610 pinctrl->functions = nsp_pin_functions; in nsp_pinmux_probe()
611 pinctrl->num_functions = ARRAY_SIZE(nsp_pin_functions); in nsp_pinmux_probe()
615 pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &nsp_pinctrl_desc, in nsp_pinmux_probe()
616 pinctrl); in nsp_pinmux_probe()
617 if (IS_ERR(pinctrl->pctl)) { in nsp_pinmux_probe()
618 dev_err(&pdev->dev, "unable to register nsp IOMUX pinctrl\n"); in nsp_pinmux_probe()
619 return PTR_ERR(pinctrl->pctl); in nsp_pinmux_probe()
622 return 0; in nsp_pinmux_probe()
626 { .compatible = "brcm,nsp-pinmux" },
632 .name = "nsp-pinmux",